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publication number S25FL512S_00 revision 07 issue date january 8, 2014 S25FL512S S25FL512S cover sheet 512 mbit (64 mbyte) mirrorbit ? flash non-volatile memory cmos 3.0 volt core with versatile i/o serial peripheral inte rface with multi-i/o data sheet notice to readers: this document states the current techni cal specifications regarding the spansion ? product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. dee ms the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. however, typographical or specificati on corrections, or modifications to the valid com- binations offered may occur. publication number S25FL512S_00 revision 07 issue date january 8, 2014 features ? density ? 512 mbits (64 mbytes) ? serial peripheral interface (spi) ? spi clock polarity and phase modes 0 and 3 ? double data rate (ddr) option ? extended addressing: 32-bit address ? serial command set and footprint compatible with s25fl-a, s25fl-k, and s25fl-p spi families ? multi i/o command set and footprint compatible with s25fl-p spi family ? read commands ? normal, fast, dual, quad, fast ddr, dual ddr, quad ddr ? autoboot - power up or reset and execute a normal or quad read command automatically at a preselected address ? common flash interface (cfi) data for configuration information. ? programming (1.5 mbytes/s) ? 512-byte page programming buffer ? quad-input page programming (qpp) for slow clock systems ? erase (0.5 to 0.65 mbytes/s) ? uniform 256-kbyte sectors ? cycling endurance ? 100,000 program-erase cycles on any sector typical ? data retention ? 20 year data retention typical ? security features ? one time program (otp) array of 1024 bytes ? block protection: ? status register bits to control protection against program or erase of a contiguous range of sectors. ? hardware and software control options ? advanced sector protection (asp) ? individual sector protection controlled by boot code or password ? spansion ? 65 nm mirrorbit technology with eclipse ? architecture ? core supply voltage: 2.7v to 3.6v ? i/o supply voltage: 1.65v to 3.6v ? so16 and fbga packages ? temperature range: ? industrial (-40 c to +85 c) ? automotive in-cabin (-40 c to +105 c) ? packages (all pb-free) ? 16-lead soic (300 mil) ? bga-24 6 x 8 mm ? 5 x 5 ball (fab024) and 4 x 6 ball (fac024) footprint options ? known good die and known tested die S25FL512S 512 mbit (64 mbyte) mirrorbit ? flash non-volatile memory cmos 3.0 volt core with versatile i/o serial peripheral inte rface with multi-i/o data sheet
4 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 1. performance summary table 1.1 maximum read rates with the same core and i/o voltage (v io = v cc = 2.7v to 3.6v) command clock rate (mhz) mbytes/s read 50 6.25 fast read 133 16.6 dual read 104 26 quad read 104 52 table 1.2 maximum read ra tes with lower i/o voltage (v io = 1.65v to 2.7v, v cc = 2.7v to 3.6v) command clock rate (mhz) mbytes/s read 50 6.25 fast read 66 8.25 dual read 66 16.5 quad read 66 33 table 1.3 maximum read rates ddr (v io = v cc = 3v to 3.6v) command clock rate (mhz) mbytes/s fast read ddr 80 20 dual read ddr 80 40 quad read ddr 80 80 table 1.4 typical program and erase rates operation kbytes/s page programming (512-byte page buffer - uniform sector option) 1500 256-kbyte logical sector erase (uniform sector option) 500 table 1.5 current consumption operation current (ma) serial read 50 mhz 16 (max) serial read 133 mhz 33 (max) quad read 104 mhz 61 (max) program 100 (max) erase 100 (max) standby 0.07 (typ)
january 8, 2014 S25FL512S_00_07 S25FL512S 5 data sheet table of contents features 1. performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 migration notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 other resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 hardware interface 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 3.1 input/output summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 address and data configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 chip select (cs#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 serial input (si) / io0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 serial output (so) / io1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 write protect (wp#) / io2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 hold (hold#) / io3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 core voltage supply (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 versatile i/o power supply (v io ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 supply and signal ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 not connected (nc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 reserved for future use (rfu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 do not use (dnu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.16 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4. signal protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 spi clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 command protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 interface states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4 configuration register effects on the interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 5.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6. timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4 sdr ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5 ddr ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7. physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1 soic 16-lead package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2 fab024 24-ball bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3 fac024 24-ball bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 software interface 8. address space maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.2 flash memory array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.3 id-cfi address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.4 jedec jesd216 serial flash disco verable parameters (sfdp) space. . . . . . . . . . . . . . . 55 8.5 otp address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 9. data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 secure silicon region (otp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2 write enable command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.3 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.4 advanced sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.1 command set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.2 identification commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.3 register access commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.4 read memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.5 program flash array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.6 erase flash array commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 10.7 one time program array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.8 advanced sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.9 reset commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.10 embedded algorithm performance tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11. software interface reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.1 command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.2 serial flash discoverable parameters (sfdp) address map . . . . . . . . . . . . . . . . . . . . . . . 120 11.3 device id and common flash interface (id-cfi) addr ess map . . . . . . . . . . . . . . . . . . . . . 122 11.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.5 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 ordering information 12. ordering information fl512s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13. contacting spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 14. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
january 8, 2014 S25FL512S_00_07 S25FL512S 7 data sheet figures figure 3.1 hold mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3.2 bus master and memory devices on the spi bus ? single bit data path . . . . . . . . . . . . . . 20 figure 3.3 bus master and memory devices on the spi bus ? dual bit data path . . . . . . . . . . . . . . . 20 figure 3.4 bus master and memory devices on the spi bus ? quad bit data path . . . . . . . . . . . . . . 20 figure 4.1 spi sdr modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4.2 spi ddr modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4.3 stand alone instruction command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4.4 single bit wide input command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4.5 single bit wide output command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4.6 single bit wide i/o command without latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4.7 single bit wide i/o command with latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 4.8 dual output command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4.9 quad output command without latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 4.10 dual i/o command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4.11 quad i/o command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4.12 ddr fast read with ehplc = 00b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4.13 ddr dual i/o read with ehplc = 01b and dlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4.14 ddr quad i/o read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 5.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 figure 5.3 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 5.4 power-down and voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 6.1 waveform element meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6.2 input, output, and timing reference levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6.3 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6.4 reset low at the end of por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6.5 reset high at the end of por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6.6 por followed by hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6.7 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 6.8 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 6.9 spi single bit input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6.10 spi single bit output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6.11 spi sdr mio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6.12 hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6.13 wp# input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6.14 spi ddr input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6.15 spi ddr output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6.16 spi ddr data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 7.1 16-lead soic package, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 7.2 24-ball bga, 5 x 5 ball footprint (fab024), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 7.3 24-ball bga, 4 x 6 ball footprint (fac024), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 8.1 otp address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9.1 advanced sector protection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 10.1 read_id (90h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 figure 10.2 read identification (rdid 9fh) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 10.3 read electronic signature (res abh) command seq uence . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 10.4 rsfdp command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 10.5 read status register-1 (rdsr1 05h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10.6 read status register-2 (rdsr2 07h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10.7 read configuration register (rdcr 35h) command sequence . . . . . . . . . . . . . . . . . . . . . 80 figure 10.8 read bank register (brrd 16h) command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 10.9 bank register write (brwr 17h) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 10.10 brac (b9h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 10.11 write registers (wrr 01h) command sequence ? 8 data bits . . . . . . . . . . . . . . . . . . . . . . 82
8 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.12 write registers (wrr 01h) command sequence ? 16 data bits . . . . . . . . . . . . . . . . . . . . . 82 figure 10.13 write enable (wren 06h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 10.14 write disable (wrdi 04h) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 10.15 clear status register (clsr 30h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 10.16 autoboot sequence (cr1[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 10.17 autoboot sequence (cr1[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 10.18 autoboot register read (abrd 14h) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 10.19 autoboot register write (abwr) command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 10.20 program nvdlr (pnvdlr 43h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 10.21 write vdlr (wvdlr 4ah) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 10.22 dlp read (dlprd 41h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 10.23 read command sequence (read 03h or 13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 10.24 fast read (fast_read 0bh or 0ch) command sequence with read latency . . . . . . . . . 90 figure 10.25 fast read command (fast_read 0bh or 0ch) sequence without read latency . . . . . . 91 figure 10.26 dual output read command sequence (3-byte address, 3bh [extadd=0], lc=10b). . . . . 91 figure 10.27 dual output read command sequence (4-byte address, 3ch or 3bh [extadd=1, lc=10b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 figure 10.28 dual output read command sequence (4-byte address, 3ch or 3bh [extadd=1, lc=11b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 10.29 quad output read (qor 6bh or 4qor 6c h) command sequence with read latency . . . 93 figure 10.30 quad output read (qor 6bh or 4qor 6ch) command sequence without read latency 93 figure 10.31 dual i/o read command sequence (3-byte address, bbh [extadd=0], hplc=00b) . . . . . 94 figure 10.32 dual i/o read command sequence (4-byte address, bbh [extadd=1], hplc=10b) . . . . . 95 figure 10.33 dual i/o read command sequence (4-byte address, bch or bbh [extadd=1], ehplc=10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 figure 10.34 continuous dual i/o read command sequence (4-byte address, bch or bbh [extadd=1], ehplc=10b) . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 10.35 quad i/o read command sequence (3-byte address, ebh [extadd=0], lc=00b) . . . . . . . 96 figure 10.36 continuous quad i/o read command sequence (3-byte address), lc=00b . . . . . . . . . . . 97 figure 10.37 quad i/o read command sequence (4-byte address, ech or ebh [extadd=1], lc=00b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 figure 10.38 continuous quad i/o read command sequence (4-byte address), lc=00b . . . . . . . . . . . 97 figure 10.39 ddr fast read initial access (3-byte addre ss, 0dh [extadd=0, ehplc=11b]) . . . . . . . . . 99 figure 10.40 continuous ddr fast read subsequent access (3-byte address [extadd=0, ehplc=11b]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 10.41 ddr fast read initial access (4-byte addr ess, 0eh or 0dh [extadd=1], ehplc=01b). . . . 99 figure 10.42 continuous ddr fast read subsequent access (4-byte address [extadd=1], ehplc=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 10.43 ddr fast read subsequent access (4-byte address, hplc=01b) . . . . . . . . . . . . . . . . . . 100 figure 10.44 ddr dual i/o read initial access (4-byte address, beh or bdh [extadd=1], ehplc= 01b) . . . . . . . . . . . . . . . . . . . . . . . . . .101 figure 10.45 continuous ddr dual i/o read subsequent access (4-byte address, ehplc= 01b) . . . 101 figure 10.46 ddr dual i/o read (4-byte address, beh or bdh [extadd=1], hplc=00b) . . . . . . . . . . . 102 figure 10.47 ddr quad i/o read initial access (3-byte ad dress, edh [extadd=0], hplc=11b). . . . . . 103 figure 10.48 continuous ddr quad i/o read subsequent access (3-byte address,hplc=11b) . . . . . 104 figure 10.49 ddr quad i/o read initial access (4-byte address, eeh or edh [extadd=1], ehplc=01b) . . . . . . . . . . . . . . . . . . . . . . . . . . .104 figure 10.50 continuous ddr quad i/o read subsequent access (4-byte address, ehplc=01b) . . . 104 figure 10.51 page program (pp 02h or 4pp 12h) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 10.52 quad 512-byte page program command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 10.53 program suspend (pgsp 85h) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 10.54 10.55 program resume (pgrs 8ah) command seq uence . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 10.55 sector erase (se d8h or 4se dch) command sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 10.56 bulk erase command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 10.57 erase suspend (ersp 75h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 10.58 erase resume (errs 7ah) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
january 8, 2014 S25FL512S_00_07 S25FL512S 9 data sheet figure 10.59 page program (otpp 42h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 10.60 read otp (otpr 4bh) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 10.61 asprd command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 10.62 aspp (2fh) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 10.63 dybrd command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 10.64 dybwr (e1h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 figure 10.65 ppbrd (e2h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 13 figure 10.66 ppbp (e3h ) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 10.67 ppb erase (ppbe e4h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 10.68 ppb lock regi ster read command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 10.69 ppb lock bit write (plbwr a6h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 10.70 password read (passrd e7h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 10.71 password program (passp e8h) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 10.72 password unlock (passu e9h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 10.73 software reset (reset f0h) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 10.74 mode bit (mbr ffh) reset command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet tables table 1.1 maximum read rates with the same core and i/o voltage (v io = v cc = 2.7v to 3.6v) . . . . 4 table 1.2 maximum read rates with lower i/o voltage (v io = 1.65v to 2.7v, v cc = 2.7v to 3.6v) . . . 4 table 1.3 maximum read rates ddr (v io = v cc = 3v to 3.6v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1.4 typical program and erase rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1.5 current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2.1 fl generations comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.1 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4.1 interface states summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.2 power-up / power-down voltage and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 6.1 ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6.2 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6.3 hardware reset parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 6.4 ac characteristics (single die package, v io = v cc 2.7v to 3.6v) . . . . . . . . . . . . . . . . . . . . 41 table 6.5 ac characteristics (single die package, v io 1.65v to 2.7v, v cc 2.7v to 3.6v) . . . . . . . . . . 42 table 6.6 ac characteristics ddr operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 7.1 model specific connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 8.1 S25FL512S sector and memory address map, uniform 256-kbyte sectors . . . . . . . . . . . . . 54 table 8.2 otp address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 8.3 status register-1 (sr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 8.4 configuration register (cr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 8.5 latency codes for sdr high performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 8.6 latency codes for ddr high performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 8.7 latency codes for sdr enhanced high performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 8.8 latency codes for ddr enhanced high performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 8.9 status register-2 (sr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 8.10 autoboot register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 8.11 bank address register (bar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 8.12 asp register (aspr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8.13 password register (pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8.14 ppb lock register (ppbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8.15 ppb access register (ppbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 8.16 dyb access register (dybar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 8.17 non-volatile data learning register (nvdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 8.18 volatile data learning register (nvdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 9.1 upper array start of protection (tbprot = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 9.2 lower array start of protection (tbprot = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 9.3 sector protection states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 10.1 bank address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 10.2 S25FL512S command set (sorted by function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 10.3 read_id values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 10.4 res values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 10.5 block protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 10.6 commands allowed during program or erase suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 10.7 program and erase performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 10.8 program suspend ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 10.9 erase suspend ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 11.1 S25FL512S instruction set (sorted by instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 11.2 sfdp overview map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 11.3 sfdp header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 11.4 manufacturer and device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 11.5 cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 11.6 cfi system interface string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
january 8, 2014 S25FL512S_00_07 S25FL512S 11 data sheet table 11.7 device geometry definition for 512-mbit device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 11.8 cfi primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 11.9 cfi alternate vendor-specific extended query header . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 11.10 cfi alternate vendor-specific extended query parameter 0 . . . . . . . . . . . . . . . . . . . . . . . 125 table 11.11 cfi alternate vendor-specific extended query parameter 80h address options . . . . . . . 125 table 11.12 cfi alternate vendor-specific extended query parameter 84h suspend commands . . . . 126 table 11.13 cfi alternate vendor-specific extended query parameter 88h data protection . . . . . . . . 126 table 11.14 cfi alternate vendor-specific extended query parameter 8ch reset timing . . . . . . . . . . 126 table 11.15 cfi alternate vendor-specific extended query parameter 90h - hplc(sdr) . . . . . . . . . . 127 table 11.16 cfi alternate vendor-specific extended query parameter 9ah - hplc ddr . . . . . . . . . . 129 table 11.17 cfi alternate vendor-specific extended query parameter 90h - ehplc (sdr) . . . . . . . . 130 table 11.18 cfi alternate vendor-specific extended query parameter 9ah - ehplc ddr . . . . . . . . . 132 table 11.19 cfi alternate vendor-specific extended query parameter f0h rfu . . . . . . . . . . . . . . . . . 133 table 11.20 status register-1 (sr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 11.21 configuration register (cr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 11.22 status register-2 (sr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 11.23 bank address register (bar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 11.24 asp regi ster (aspr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 11.25 password re gister (pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 11.26 ppb lock regi ster (ppbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 11.27 ppb access register (ppbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 11.28 dyb access register (dybar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 11.29 non-volatile data learning register (nvdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 11.30 volatile data learning register (nvdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 11.31 asp regist er content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 2. overview 2.1 general description the spansion S25FL512S device is a flas h non-volatile memory product using: ? mirrorbit technology - that stores two da ta bits in each memory array transistor ? eclipse architecture - that dramatically improves program and erase performance ? 65 nm process lithography this device connects to a host system via a serial peripheral in terface (spi). traditional spi single bit serial input and output (single i/o or sio) is supported as well as optional two bit (dual i/o or dio) and four bit (quad i/o or qio) serial commands. this multiple width interface is called spi multi-i/o or mio. in addition, the fl-s family adds support for double data rate (ddr) read commands for sio, dio, and qio that transfer address and read data on both edges of the clock. the eclipse architecture features a page programming bu ffer that allows up to 256 words (512 bytes) to be programmed in one operation, resulting in faster e ffective programming and erase than prior generation spi program or erase algorithms. executing code directly from flash me mory is often called execute-in-place or xip. by using fl-s devices at the higher clock rates supported, with qio or ddr-qio commands, the in struction read transfer rate can match or exceed traditional parallel interface, asynchronous, nor flash memories while reducing signal count dramatically. the S25FL512S product offers high densities coupled wit h the flexibility and fast performance required by a variety of embedded applications. it is idea l for code shadowing, xip, and data storage.
january 8, 2014 S25FL512S_00_07 S25FL512S 13 data sheet 2.2 migration notes 2.2.1 features comparison the S25FL512S device is command set and footprin t compatible with prior generation fl-k and fl-p families. notes: 1. 256b program page option only for 128-mb and 256-mb density fl-s devices. 2. fl-p column indicates fl129p mio spi device (for 128-mb density). 3. 64 kb sector erase option only for 128-mb/256-mb density fl-p and fl-s devices. 4. fl-k family devices can erase 4-kb sectors in groups of 32 kb or 64 kb. 5. refer to individual data sheets for further details. 2.2.2 known differences from prior generations 2.2.2.1 error reporting prior generation fl memories either do not have error st atus bits or do not set them if program or erase is attempted on a protected sector. the fl -s family does have error reporting status bits for program and erase operations. these can be set when there is an internal fail ure to program or erase or when there is an attempt to program or erase a protected sect or. in either case the program or erase operation did not complete as requested by the command. 2.2.2.2 secure silicon region (otp) the size and format (address map) of the one time pr ogram area is different from prior generations. the method for protecting each portion of the otp area is different. for additional details see secure silicon region (otp) on page 65 . table 2.1 fl generations comparison parameter fl-k fl-p fl-s technology node 90 nm 90 nm 65 nm architecture floating gate mirrorbit mirrorbit eclipse release date in production in production in production density 4 mb - 128 mb 32 mb - 256 mb 512 mb bus width x1, x2, x4 x1 , x2, x4 x1, x2, x4 supply voltage 2.7v - 3.6v 2.7v - 3.6v 2.7v - 3.6v / 1.65v - 3.6v v io normal read speed (sdr) 6 mb/s (50 mh z) 5 mb/s (40 mhz) 6 mb/s (50 mhz) fast read speed (sdr) 13 mb/s (104 mhz) 13 mb/s (104 mhz) 17 mb/s (133 mhz) dual read speed (sdr) 26 mb/s (104 mhz) 20 mb/s (80 mhz) 26 mb/s (104 mhz) quad read speed (sdr) 52 mb/s (104 mhz) 40 mb/s (80 mhz) 52 mb/s (104 mhz) fast read speed (ddr) - - 20 mb/s (80 mhz) dual read speed (ddr) - - 40 mb/s (80 mhz) quad read speed (ddr) - - 80 mb/s (80 mhz) program buffer size 256b 256b 512b erase sector size 4 kb / 32 kb / 64 kb 64 kb / 256 kb 256 kb parameter sector size 4 kb 4 kb ? sector erase time (typ.) 30 ms (4 kb), 150 ms (64 kb) 500 ms (64 kb) 520 ms (256 kb) page programming time (typ.) 700 s (256b) 1500 s (256b) 340 s (512b) otp 768b (3 x 256b) 506b 1024b advanced sector protection no no yes auto boot mode no no yes erase suspend/resume yes no yes program suspend/resume yes no yes operating temperature ?40c to +85c ?40c to +85c / +105 c ?40c to +85c / +105 c
14 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 2.2.2.3 configuration register freeze bit the configuration register freeze bit cr1[0], locks th e state of the block protection bits as in prior generations. in the fl-s family it also locks the state of the configuration register tbparm bit cr1[2], tbprot bit cr1[5], and the secure silicon region (otp) area. 2.2.2.4 sector erase commands the command for erasing an 8-kbyte area (t wo 4-kbyte sectors) is not supported. the command for erasing a 4-kbyte sector is no t supported in the 512-mbit density fl-s device. the erase command for 64-kbyte sectors is not s upported in the 512-mbit density fl-s device. 2.2.2.5 deep power down the deep power down (dpd) function is not supported in fl-s family devices. the legacy dpd (b9h) command code is instead used to enable legacy spi memory controllers, that can issue the former dpd command, to access a new bank a ddress register. the bank address register allows spi memory controllers that do not support more than 24 bits of address, the ability to provide higher order address bits for commands, as needed to access the larger address space of the 256-mbit density fl-s device. for additional information see extended address on page 54 . 2.2.2.6 new features the fl-s family introduces several new features to spi category memories: ? extended address for access to higher memory density. ? autoboot for simpler access to boot code following power up. ? enhanced high performance read commands using mode bits to eliminate the overhead of sio instructions when repeating the same type of read command. ? multiple options for initial read la tency (number of dummy cycles) for fast er initial access time or higher clock rate read commands. ? ddr read commands for sio, dio, and qio. ? advanced sector protection for individually controlling th e protection of each sector. this is very similar to the advanced sector protection feature found in se veral other spansion parallel interface nor memory families.
january 8, 2014 S25FL512S_00_07 S25FL512S 15 data sheet 2.3 glossary 2.4 other resources 2.4.1 links to software http://www.spansion.com/ support/pages/support.aspx 2.4.2 links to application notes http://www.spansion.com/support/technical documents/pages/applicationnotes.aspx 2.4.3 specification bulletins specification bulletins provide information on temporar y differences in feature description or parametric variance since the publication of the last full data sheet. contact your local sales office for details. obtain the latest list of company locations and contact information at: http://www.spansion.com/about/pages/locations.aspx command all information transferred between the host system and memory during one period while cs# is low. this includes the instruction (sometimes called an operation code or opcode) and any required address, mode bits, latency cycles, or data. ddp (dual die package) two die stacked within the same package to increase the memory capacity of a single package. often also referred to as a multi-chip package (mcp). ddr (double data rate) when input and output are latched on every edge of sck. flash the name for a type of electrical erase programmable read only memory (eeprom) that erases large blocks of memory bits in paralle l, making the erase operation much faster than early eeprom. high a signal voltage level v ih or a logic level repr esenting a binary one (1). instruction the 8 bit code indicating the function to be per formed by a command (sometimes called an operation code or opcode). the instruction is al ways the first 8 bits transferred from host system to the memory in any command. low a signal voltage level v il or a logic level representing a binary zero (0). lsb (least significant bit) generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. msb (most significant bit) generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value. non-volatile no power is needed to maintain data stored in the memory. opn (ordering part number) the alphanumeric string specifying the memory device type, density, package, factory non- volatile configuration, etc. used to select the desired device. page 512 bytes aligned and length group of data. pcb printed circuit board. register bit references are in the format: register_name[bit_ number] or register_name[bit_range_msb: bit_range_lsb]. sdr (single data rate) when input is latched on the rising edge and output on the falling edge of sck. sector erase unit size 256 kbytes. write an operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same wa y that volatile data is modified ? as a single operation. the non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data.
16 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet hardware interface serial peripheral interface with multiple input / output (spi-mio) many memory devices connect to their host system with separate parallel control, address, and data signals that require a large number of signal connections and la rger package size. the large number of connections increase power consumption due to so many signals switching and the larger package increases cost. the S25FL512S device reduces the number of signal s for connection to the host system by serially transferring all control, address, and data information over 4 to 6 signals. this reduce s the cost of the memory package, reduces signal switching power, and either reduces the host connection count or frees host connectors for use in providing other features. the S25FL512S device uses the industry standard single bit serial periphera l interface (spi) and also supports optional extension commands for two bit (dua l) and four bit (quad) wide serial transfers. this multiple width interface is ca lled spi multi-i/o or spi-mio. 3. signal descriptions 3.1 input/output summary table 3.1 signal list signal name type description reset# input hardware reset: low = device resets and returns to standby state, ready to receive a command. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used. sck input serial clock. cs# input chip select. si / io0 i/o serial input for single bit data commands or io0 for dual or quad commands. so / io1 i/o serial output for single bit data commands. io1 for dual or quad commands. wp# / io2 i/o write protect when not in quad mode. io2 in quad mode. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands. hold# / io3 i/o hold (pause) serial transfer in single bit or dual data commands. io3 in quad-i/o mode. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands. v cc supply core power supply. v io supply versatile i/o power supply. v ss supply ground. nc unused not connected. no device internal signal is connec ted to the package connector nor is there any future plan to use the connecto r for a signal. the connection may safely be used for routing space for a signal on a printe d circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v io . rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. dnu reserved do not use. a device internal signal may be c onnected to the package connector. the connection may be used by spansion for test or other purposes and is not intended for connection to any host system signal. any dnu si gnal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to this connection.
january 8, 2014 S25FL512S_00_07 S25FL512S 17 data sheet 3.2 address and data configuration traditional spi single bit wide commands (single or sio) send information from the host to the memory only on the si signal. data may be sent back to the host serially on the serial output (so) signal. dual or quad output commands send information from th e host to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input/output (i/o) commands send informa tion from the host to the memory as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. 3.3 reset# the reset# input provides a hardware method of resetti ng the device to standby state, ready for receiving a command. when reset# is driven to logic low (v il ) for at least a period of t rp , the device: ? terminates any operation in progress, ? tristates all outputs, ? resets the volatile bits in the configuration register, ? resets the volatile bits in the status registers, ? resets the bank address register to zero, ? loads the program buffer with all ones, ? reloads all internal configuration information necessary to bring the device to standby mode, ? and resets the internal cont rol unit to standby state. reset# causes the same initialization process as is performed when power comes up and requires t pu time. reset# may be asserted low at any ti me. to ensure data integrity any operation that was interrupted by a hardware reset should be reinitiated once the device is ready to accept a command sequence. when reset# is first asserted low, the device draws i cc1 (50 mhz value) during t pu . if reset# continues to be held at v ss the device draws cm os standby current (i sb ). reset# has an internal pull-up resi stor and may be left unconnected in the host system if not used. the reset# input is not available on all packages op tions. when not available the reset# input of the device is tied to the inactive state, inside the package. 3.4 serial clock (sck) this input signal provides the synchronization reference fo r the spi interface. instructions, addresses, or data input are latched on the rising edge of the sck signal. da ta output changes after the falling edge of sck, in sdr commands, and after every edge in ddr commands. 3.5 chip select (cs#) the chip select signal indicates when a command for the device is in process and the other signals are relevant for the memory device. when the cs# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. unless an internal program, erase or write registers (wrr) embedded operation is in progress, the device will be in the standby power mode. driving the cs# input to logic low st ate enables the device, placing it in the active power mode. after power- up, a falling edge on cs# is required prior to the start of any command.
18 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 3.6 serial input (si) / io0 this input signal is used to transfer data serially into the device. it receives instructions, addresses, and data to be programmed. values are latched on the rising edge of serial sck clock signal. si becomes io0 - an input and output during dual and quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck, in sdr comma nds, and on every edge of sck, in ddr commands). 3.7 serial output (so) / io1 this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial sck clock signal. so becomes io1 - an input and output during dual and quad commands for receiving addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck, in sdr commands, a nd on every edge of sck, in ddr commands). 3.8 write protect (wp#) / io2 when wp# is driven low (v il ), during a wrr command and while the status register write disable (srwd) bit of the status register is set to a 1, it is not possibl e to write to the status and configuration registers. this prevents any alteration of the block protect (bp2, bp1, bp0) and tbprot bits of the status register. as a consequence, all the data bytes in the memory area that are protected by the block protect and tbprot bits, are also hardware protected against data mo dification if wp# is low during a wrr command. the wp# function is not available w hen the quad mode is enabled (cr[1]=1). the wp# function is replaced by io2 for input and output during quad mode for re ceiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck, in sdr commands, and on every edge of sck, in ddr commands). wp# has an internal pull-up resistor ; when unconnected, wp# is at v ih and may be left unconnected in the host system if not used for quad mode. 3.9 hold (hold#) / io3 the hold (hold#) signal is used to pause any serial communications with the device without deselecting the device or stopping the serial clock. to enter the hold condition, the devi ce must be selected by driving the cs # input to the logic low state. it is recommended that the user keep the cs# input low state during the entire duration of the hold condition. this is to ensure that the state of t he interface logic remains unchanged from the moment of entering the hold condition. if the cs# input is driven to the logic high state while the device is in the hold condition, the interface logic of the device will be re set. to restart communication with t he device, it is necessary to drive hold# to the logic high state while driving the cs# signa l into the logic low state. this prevents the device from going back into the hold condition. the hold condition starts on the falling edge of the ho ld (hold#) signal, provided that this coincides with sck being at the logic low state. if the falling edge does not coincide with the sck signal being at the logic low state, the hold condition starts whenever the sck signal reaches the logic low state. taking the hold# signal to the logic low state does not terminate any writ e, program or erase operation that is currently in progress. during the hold condition, so is in high imped ance and both the si and sck input are don't care. the hold condition ends on the rising edge of the hold (hold#) signal, provided that this coincides with the sck signal being at the logic low state. if the rising edge does not coincide with the sck signal being at the logic low state, the hold condition ends whenever the sck signal reaches the logic low state. the hold# function is not available when the quad m ode is enabled (cr1[1] =1). the hold function is replaced by io3 for input and output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck, in sdr commands, and on every edge of sck, in ddr commands).
january 8, 2014 S25FL512S_00_07 S25FL512S 19 data sheet the hold# signal has an internal pu ll-up resistor and may be left unconn ected in the host system if not used for quad mode. figure 3.1 hold mode operation 3.10 core voltage supply (v cc ) v cc is the voltage source for all device internal logic. it is the single voltage used for all device internal functions including read, program, and erase. the voltage may vary from 2.7v to 3.6v. 3.11 versatile i/o power supply (v io ) the versatile i/o (v io ) supply is the voltage source for all device input receivers and output drivers and allows the host system to set the voltage levels that the device tolerates on all inputs and drives on outputs (address, control, and io signals). the v io range is 1.65v to v cc . v io cannot be greater than v cc . for example, a v io of 1.65v - 3.6v allows for i/o at the 1.8v, 2. 5v or 3v levels, driving and receiving signals to and from other 1.8v, 2.5v or 3v devices on the same data bus. v io may be tied to v cc so that interface signals operate at the same voltage as the core of the device. v io is not available in all package options, when not available the v io supply is tied to v cc internal to the package. during the rise of power supplies the v io supply voltage must remain less than or equal to the v cc supply voltage. however, the v io supply voltage must also be above v cc -200 mv until the v io supply voltage is > 1.65v, i.e. the v io supply voltage must not lag behind the v cc supply voltage by more than 200 mv during power up, until the v io supply voltage reaches its minimum operating level. this supply is not available in all package options. for a backward compatible so16 footprint, the v io supply is tied to v cc inside the package; thus, the io will function at v cc level. 3.12 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference fo r the device core, input signal receivers, and output drivers. 3.13 not connected (nc) no device internal signal is connected to the pack age connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v io . 3.14 reserved for future use (rfu) no device internal signal is currently connected to th e package connector but is there potential future use of the connector. it is recommended to not use rfu connectors for pcb r outing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. cs# sck hold# si_or_io_(du ring_input) s o_or_io_(internal) s o_or_io_(external) v alid inpu t don't ca re v alid inpu t don't ca re v alid input abcde ab b c d e hold condition standard use hold condition non-standard use
20 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 3.15 do not use (dnu) a device internal signal may be connected to the package connector. the connection may be used by spansion for test or other purposes and is not inte nded for connection to any host system signal. any dnu signal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconn ected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. 3.16 block diagrams figure 3.2 bus master and memory devices on the spi bus ? single bit data path figure 3.3 bus master and memory devices on the spi bus ? dual bit data path figure 3.4 bus master and memory devices on the spi bus ? quad bit data path s pi bus master hold# wp# s o s i sck c s 2# c s 1# fl-s flash fl-s flash hold# wp# s o s i sck c s 2# c s 1# s pi bus master hold# wp# io1 io0 sck c s 2# c s 1# fl-s flash fl-s flash hold# wp# io0 io1 sck c s 2# c s 1# s pi bus master io3 io2 io1 io0 sck c s 2# c s 1# fl-s flash fl-s flash io3 io2 io0 io1 sck c s 2# c s 1#
january 8, 2014 S25FL512S_00_07 S25FL512S 21 data sheet 4. signal protocols 4.1 spi clock modes 4.1.1 single data rate (sdr) the S25FL512S device can be driven by an embedded micr ocontroller (bus master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data is always available from the falling edge of the sck clock signal. the difference between the two modes is the clock polari ty when the bus master is in standby mode and not transferring any data. ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 4.1 spi sdr modes supported timing diagrams throughout the remainder of the docu ment are generally shown as both mode 0 and 3 by showing sck as both high and low at the fall of cs#. in some cases a timing diagram may show only mode 0 with sck low at the fall of cs#. in such a case, mode 3 timing simply means clock is high at the fall of cs# so no sck rising edge set up or hold time to the falling edge of cs# is needed for mode 3. sck cycles are measured (counted) fr om one falling edge of sc k to the next falling ed ge of sck. in mode 0 the beginning of the first sc k cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already low at the beginning of a command. 4.1.2 double data rate (ddr) mode 0 and mode 3 are also supported for ddr comm ands. in ddr commands, the instruction bits are always latched on the rising edge of clock, the same as in sdr commands. however, the address and input data that follow the instruction are la tched on both the rising and falling edges of sck. the first address bit is latched on the first rising edge of sck following the falling edge at the end of the last instruction bit. the first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle. sck cycles are measured (counted) in the same way as in sdr commands, from one falling edge of sck to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already low at the beginning of a command. cpol=0_cpha=0_sck cpol=1_cpha=1_sck cs# si so msb msb
22 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 4.2 spi ddr modes supported 4.2 command protocol all communication between th e host system and S25FL512S memory device is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. commands may also have an address, instruct ion modifier, latency period, data transfer to the memory, or data transfer from the memory. all instru ction, address, and data information is transferred serially between the host system and memory device. all instructions are transferred from host to memory as a single bit serial sequence on the si signal. single bit wide commands may provide an address or data sent only on the si signal. data may be sent back to the host serially on the so signal. dual or quad output commands provide an address sent to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input/output (i/o) commands provide an ad dress sent from the host as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. commands are structured as follows: ? each command begins with cs# going low and ends with cs# returning high. the memory device is selected by the host driving the chip sele ct (cs#) signal low throughout a command. ? the serial clock (sck) marks the transfer of each bit or group of bits between the host and memory. ? each command begins with an 8-bit (byte) instruction. the instruction is always presented only as a single bit serial sequence on the serial input (si) signal with one bit transferred to the memory device on each sck rising edge. the instruction selects the type of information transfer or device operation to be performed. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. the instruct ion determines the address space used. the address may be either a 24-bit or a 32-bit byte boundary, address. the addre ss transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? the width of all transfers following the instructio n are determined by the instruction sent. following transfers may continue to be single bit serial on only t he si or serial output (so) signals, they may be done in 2-bit groups per (dual) transfer on the io0 and io1 signals, or they may be done in 4-bit groups per (quad) transfer on the io0-io3 signals. within the dual or quad groups the least si gnificant bit is on io0. more significant bits are placed in significance order on each higher numbered io signal. single bits or parallel bit groups are transferred in most to least significant bit order. cpol=0_cpha=0_sck cpol=1_cpha=1_sck cs# transfer_phase si so inst. 7 inst. 0 a31 a0 dlp7 d0 d1 dummy / dlp address mode instruction a30 m7 m6 m0 dlp0 read data
january 8, 2014 S25FL512S_00_07 S25FL512S 23 data sheet ? some instructions send an instructio n modifier called mode bits, following the address, to indicate that the next command will be of the same type with an implie d, rather than an explicit, instruction. the next command thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. the mode bit transfers occur on sck risi ng edge, in sdr commands, or on every sck edge, in ddr commands. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? sck continues to toggle during any read access latency period. the latency may be zero to several sck cycles (also referred to as dummy cycles). at the end of the read latency cycles, the first read data bits are driven from the outputs on sck falling edge at the end of the last read latency cycle. the first read data bits are considered transferred to the host on the fo llowing sck rising edge. each following transfer occurs on the next sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? if the command returns read data to the host, the devi ce continues sending data transfers until the host takes the cs# signal high. the cs# signal can be driven high after any transfer in the read data sequence. this will terminate the command. ? at the end of a command that does not return data, the host drives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone inst ruction or, of the last write data byte that is transferred. that is, the cs# signal must be driven high when the number of clock cycles after cs# signal was driven low is an exact multiple of eight cycles. if the cs# signal does not go high exac tly at the eight sck cycle boundary of the instruction or write dat a, the command is reje cted and not executed. ? all instruction, address, and mode bits are shifted into the device with the most significant bits (msb) first. the data bits are shifted in and out of the device msb first. all data is transferred in byte units with the lowest address byte sent first. following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. ? all attempts to read the flash memory array duri ng a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will c ontinue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful.
24 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 4.2.1 command sequence examples figure 4.3 stand alone instruction command figure 4.4 single bit wide input command figure 4.5 single bit wide output command figure 4.6 single bit wide i/o command without latency figure 4.7 single bit wide i/o command with latency cs# sck si so phase 76543210 instruction cs# sck si so phase 7654321076543210 instruction input data cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 instruction dummy cycles data 1 address
january 8, 2014 S25FL512S_00_07 S25FL512S 25 data sheet figure 4.8 dual output command figure 4.9 quad output comma nd without latency figure 4.10 dual i/o command figure 4.11 quad i/o command cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 28 26 0 6 4 2 0 6 4 2 0 31 29 27 1 7 5 3 1 7 5 3 1 instruction 6 dummy data 1 data 2 address cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 31 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address data 1 data 2 data 3 data 4 data 5 ... cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0 31 3 1 7 5 3 1 7 5 3 1 instruction address dummy data 1 data 2 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 4 0 4 4 0 4 0 4 0 4 0 29 5 1 5 5 1 5 1 5 1 5 1 30 6 2 6 6 2 6 2 6 2 6 2 31 7 3 7 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4
26 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 4.12 ddr fast read with ehplc = 00b figure 4.13 ddr dual i/o read with ehplc = 01b and dlp figure 4.14 ddr quad i/o read additional sequence diagrams, specific to each command, are provided in section 10., commands on page 71 . cs# sck si so phase 7 6 5 4 3 2 1 0 31 30 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address mode dummy data 1 data 2 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 28 0 6 4 2 0 7 6 5 4 3 2 1 0 6 4 2 0 6 31 29 1 7 5 3 1 7 6 5 4 3 2 1 0 7 5 3 1 7 instruction mode dum dlp data 1 address cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address dummy dlp d1 d2 mode
january 8, 2014 S25FL512S_00_07 S25FL512S 27 data sheet 4.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend: z = no driver - floating signal hl = host driving v il hh = host driving v ih hv = either hl or hh table 4.1 interface states summary interface state v cc v io reset# sck cs# hold# / io3 wp# / io2 so / io1 si / io0 power-off 28 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet x = hl or hh or z ht = toggling between hl and hh ml = memory driving v il mh = memory driving v ih mv = either ml or mh 4.3.1 power-off when the core supply voltage is at or below the v cc (low) voltage, the device is co nsidered to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. 4.3.2 low power hardware data protection when v cc is less than v cc (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. 4.3.3 power-on (cold) reset when the core voltage supply remains at or below the v cc (low) voltage for t pd time, then rises to v cc (minimum) the device will begin its power-on reset (por) process. por continues until the end of t pu . during t pu the device does not react to external input si gnals nor drive any outputs. following the end of t pu the device transitions to the inte rface standby state and can accept commands. for additional information on por see power-on (cold) reset on page 38 . 4.3.4 hardware (warm) reset some of the device package options provide a reset# input. when reset# is driven low for t rp time the device starts the hardware reset process. the process continues for t rph time. following the end of both t rph and the reset hold time foll owing the rise of reset# (t rh ) the device transitions to the interface standby state and can accept commands. for additional information on hardware reset see por followed by hardware reset on page 39 . 4.3.5 interface standby when cs# is high the spi interface is in standby st ate. inputs other than reset# are ignored. the interface waits for the beginning of a new command. the next inte rface state is instruction cycle when cs# goes low to begin a new command. while in interface standby state the memory device draws standby current (i sb ) if no embedded algorithm is in progress. if an embedded algorithm is in progre ss, the related current is drawn until the end of the algorithm when the entire device returns to standby current draw. 4.3.6 instruction cycle when the host drives the msb of an instruction and cs# goes low, on the next rising edge of sck the device captures the msb of the in struction that begins the new command. on each following rising edge of sck the device captures the next lower significance bit of the 8 bit instruction. the host ke eps reset# high, cs# low, hold# high, and drives write protect (wp#) signal as needed for the instruction. however, wp# is only relevant during instruction cycles of a wrr command and is otherwise ignored. each instruction selects the address space that is operated on and the transfer format used during the remainder of the command. the transfer format may be single, dual output, quad output, dual i/o, quad i/o, ddr single i/o, ddr dual i/o, or ddr quad i/o. the expected next interface state depends on the instruction received. some commands are stand alone, needing no address or data transfer to or from the memory. the host returns cs# high after the rising edge of sck for the eight h bit of the instruction in such commands. the next interface state in this case is interface standby.
january 8, 2014 S25FL512S_00_07 S25FL512S 29 data sheet 4.3.7 hold when quad mode is not enabled (cr[1]=0) the hold# / io3 signal is used as the hold# input. the host keeps reset# high, hold# low, sck ma y be at a valid level or contin ue toggling, and cs # is low. when hold# is low a command is paused, as though sck we re held low. si / io0 and so / io1 ignore the input level when acting as inputs and are high impedance when acting as outputs during hold state. whether these signals are input or output depends on the command and the point in the command sequence when hold# is asserted low. when hold# returns high the next state is the same state the interface was in just before hold# was asserted low. when quad mode is enabled the hold# / io3 signal is used as io3. during ddr commands the hold# and wp# inputs are ignored. 4.3.8 single input cycle - host to memory transfer several commands transfer info rmation after the instruction on the single serial input (si) signal from host to the memory device. the dual output, and quad output commands send address to the memory using only si but return read data using the i/o signals. the host keeps r eset# high, cs# low, hold # high, and drives si as needed for the command. the memory does not drive the serial output (so) signal. the expected next interface state depends on the instruct ion. some instructions continue sending address or data to the memory using additional single input cycles. others may transition to single latency, or directly to single, dual, or quad output. 4.3.9 single latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to the host. the numbe r of latency cycles are determined by the latency code in the configuration register (cr[ 7:6]). during the latency cycles, the host keeps reset# high, cs# low, and hold# high. the write protect (wp#) si gnal is ignored. the host may drive the si signal during these cycles or the host may leave si floating. the memory does not use any data driven on si / i/o0 or other i/o signals during the latency cycles. in dual or quad read commands, the host mu st stop driving the i/o signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving i/o signals during latency cycles so that there is sufficie nt time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. th is prevents driver conflict between host and memory when the signal direction changes. the me mory does not drive the seri al output (so) or i/o signa ls during the latency cycles. the next interface state dep ends on the command struct ure i.e. the numb er of latency cycl es, and whether the read is single, dual, or quad width. 4.3.10 single output cycle - memory to host transfer several commands transfer information back to the hos t on the single serial output (so) signal. the host keeps reset# high, cs# low, and ho ld# high. the write prot ect (wp#) signal is ignored. the memory ignores the serial input (si) sign al. the memory drives so with data. the next interface state continues to be single output cycle until the ho st returns cs# to high ending the command. 4.3.11 dual input cycle - host to memory transfer the read dual i/o command transfers two address or mode bits to the memory in each cycle. the host keeps reset# high, cs# low, hold# high. the write protect (wp#) signal is ignored. the host drives address on si / io0 and so / io1. the next interface state following the de livery of address and mode bits is a dual latency cycle if there are latency cycles needed or dual output cycle if no latency is required.
30 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 4.3.12 dual latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to the host. the numbe r of latency cycles are determined by the latency code in the configuration register (cr[ 7:6]). during the latency cycles, the host keeps reset# high, cs# low, and hold# high. the write protect (wp#) signal is ignor ed. the host may drive the si / io0 and so / io1 signals during these cycles or the host may leave si / io0 and so / io1 floating. the memory does not use any data driven on si / io0 and so / io1 during the latency cycl es. the host must stop driving si / io0 and so / io1 on the falling edge at t he end of the last latency cycle. it is re commended that the host stop driving them during all latency cycles so t hat there is sufficient time for the host drivers to tu rn off before the memory begins to drive at the end of the latency cycles. this prevents driver conflict between host and memory when the signal direction changes. the memory does not driv e the si / io0 and so / io1 signals during the latency cycles. the next interface state follo wing the last latency cycle is a dual output cycle. 4.3.13 dual output cycle - memory to host transfer the read dual output and read dual i/o return data to the host two bits in each cycle. the host keeps reset# high, cs# low, and hold# high. the write prot ect (wp#) signal is ignored. the memory drives data on the si / io0 and so / io1 signa ls during the dual output cycles. the next interface state continues to be dual output cycle until the host returns cs# to high ending the command. 4.3.14 qpp or qor ad dress input cycle the quad page program and quad output read commands send address to the memory only on io0. the other io signals are ignored because the device must be in quad mode for these commands thus the hold and write protect features are not active. the host keeps reset# high, cs# low, and drives io0. for qpp the next interface state following th e delivery of address is the quad input cycle. for qor the next interface state following address is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. 4.3.15 quad input cycle - host to memory transfer the quad i/o read command tr ansfers four address or mode bits to the memory in each cycle. the quad page program command transfe rs four data bits to the memory in each cycle. the host keeps reset# high, cs# low, and drives the io signals. for quad i/o read the next interface state following the delivery of address and mode bits is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. for quad page program the host returns cs# high following the delivery of data to be programmed and the interface returns to standby state. 4.3.16 quad latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to the host. the numbe r of latency cycles are determined by the latency code in the configuration regist er (cr[7:6]). during the latency cycles, the host keeps reset# high, cs# low. the host may drive the io signals during these cycles or the host may leave the io floa ting. the memory does not use any data driven on io during the latency cycles. the host must stop driving the io signals on the falling edge at the end of the last latency cycle. it is recommended that the host st op driving them during all latency cycles so that there is sufficient time for the host driv ers to turn off before the memory begins to drive at the end of the latency cycles. this prevents driver conflict between host and memory when the signal di rection changes. the memory does not drive the io signals during the latency cycles. the next interface state follo wing the last latency cycle is a quad output cycle.
january 8, 2014 S25FL512S_00_07 S25FL512S 31 data sheet 4.3.17 quad output cycle - memory to host transfer the quad output read and quad i/o read return data to the host four bits in each cycle. the host keeps reset# high, and cs# low. the memory drives dat a on io0-io3 signals during the quad output cycles. the next interface state continues to be quad output cycle until the host returns cs# to high ending the command. 4.3.18 ddr single input cycl e - host to memory transfer the ddr fast read command sends address, and mode bits to the memory only on the io0 signal. one bit is transferred on the rising edge of sck and one bit on the falling edge in each cycle. the host keeps reset# high, and cs# low. the other io signals are ignored by the memory. the next interface state following the delivery of address and mode bits is a ddr latency cycle. 4.3.19 ddr dual input cycle - host to memory transfer the ddr dual i/o read command sends address, and mode bits to the memory only on the io0 and io1 signals. two bits are transferred on the rising edge of sck and two bits on the falling edge in each cycle. the host keeps reset# high, and cs# low. the io2 and io3 signals are i gnored by the memory. the next interface state following the delivery of address and mode bits is a ddr latency cycle. 4.3.20 ddr quad input cycle - host to memory transfer the ddr quad i/o read command sends address, and mode bits to the memory on all the io signals. four bits are transferred on the rising edge of sck and four bits on the falling edge in each cycle. the host keeps reset# high, and cs# low. the next interface state following the delivery of address and mode bits is a ddr latency cycle. 4.3.21 ddr latency cycle ddr read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the configuration register (cr[7:6]). during the latency cycles, the host keeps reset# high and cs# low. the host may not drive the io signals during these cycles. so that there is sufficient time for the host drivers to turn off before the memory begins to driv e. this prevents driver conflict between host and memory when the signal direction changes. the memory has an option to drive all the io signals with a data learning pattern (dlp) during the last 4 latency cycles. the dl p option should not be enabled when there are fewer than five latency cycles so that there is at least one cycl e of high impedance for turn around of the io signals before the memory begins driving the dlp. when there are more than 4 cycles of latency the memory does not drive the io signa ls until the last four cycles of latency. the next interface state following t he last latency cycle is a ddr single, dual, or quad output cycle, depending on the instruction. 4.3.22 ddr single ou tput cycle - memory to host transfer the ddr fast read command returns bits to the host only on the so / io1 signal. one bit is transferred on the rising edge of sck and one bit on the falling edge in each cycle. the host keeps reset# high, and cs# low. the other io signals are not driven by the memory. the next interface state continues to be ddr single out put cycle until the host returns cs# to high ending the command. 4.3.23 ddr dual output cycl e - memory to host transfer the ddr dual i/o read command returns bits to the host only on the io0 and io1 signals. two bits are transferred on the rising edg e of sck and two bits on the falling edge in each cyc le. the host keeps reset# high, and cs# low. the io2 and io3 signals are not driven by the memory. the next interface state continues to be ddr dual output cycle until the host returns cs# to high ending the command.
32 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 4.3.24 ddr quad output cycle - memory to host transfer the ddr quad i/o read command returns bits to the host on all the io signals. four bits are transferred on the rising edge of sck and four bits on the falling edge in each cycle. the host keeps reset# high, and cs# low. the next interface state continues to be ddr quad output cycle until the host returns cs# to high ending the command. 4.4 configuration register effects on the interface the configuration register bits 7 and 6 (cr1[7:6]) sele ct the latency code for all read commands. the latency code selects the number of mode bit and la tency cycles for each type of instruction. the configuration register bit 1 (cr1[1]) selects whether quad mode is enabled to ignore hold# and wp# and allow quad page program, quad output read, and quad i/o read commands. quad mode must also be selected to allow read ddr quad i/o commands. 4.5 data protection some basic protection against unint ended changes to stored data are provided and controlled purely by the hardware design. these are described below. other software managed protection methods are discussed in the software section ( page 54 ) of this document. 4.5.1 power-up when the core supply voltage is at or below the v cc (low) voltage, the device is co nsidered to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. program and erase operations continue to be prevented during the power-on reset (por) because no command is accepted until the exit from por to the interface standby state. 4.5.2 low power when v cc is less than v cc (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. 4.5.3 clock pulse count the device verifies that all program, erase, and wr ite registers (wrr) commands consist of a clock pulse count that is a multiple of eight before executing them. a command not having a multiple of 8 clock pulse count is ignored and no error st atus is set for the command.
january 8, 2014 S25FL512S_00_07 S25FL512S 33 data sheet 5. electrical specifications 5.1 absolute maximum ratings notes: 1. v io must always be less than or equal v cc + 200 mv. 2. see input signal overshoot on page 34 for allowed maximums during signal transition. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 5.2 operating ranges operating ranges define those limits between whic h the functionality of th e device is guaranteed. 5.2.1 temperature ranges industrial (i) devices ambient temperature (t a ) ....................................... ?40c to +85c automotive (a) in-cabin ambient temperature (t a ) ....................................... ?40c to +105c automotive operating and performance parameters wil l be determined by device characterization and may vary from standard industrial temperature range devi ces as currently shown in this specification. 5.2.2 power supply voltages some package options provide access to a separate input and output buffer power supply called v io . packages which do not provide the separate v io connection, internally connect the device v io to v cc . for these packages the references to v io are then also references to v cc . v cc ?????2.7v to 3.6v v io ...................1.65v to v cc + 200 mv table 5.1 absolute maximum ratings storage temperature plastic packages ?65c to +150 c ambient temperature with power applied ?65c to +125 c v cc ?0.5v to +4.0v v io (note 1) ?0.5v to +4.0v input voltage with respect to ground (v ss ) (note 2) ?0.5v to +(v io + 0.5v) output short circuit current (note 3) 100 ma
34 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 5.2.3 input si gnal overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v io . during voltage transitions, inputs or i/os may overshoot v ss to ?2.0v or overshoot to v io +2.0v, for periods up to 20 ns. figure 5.1 maximum negative overshoot waveform figure 5.2 maximum positive overshoot waveform 5.3 power-up and power-down the device must not be selected at power-up or power-dow n (that is, cs# must follow the voltage applied on v cc ) until v cc reaches the correct value as follows: ? v cc (min) at power-up, and then for a further delay of t pu ? v ss at power-down a simple pull-up resistor (generally of the order of 100 k ) on chip select (cs#) can usually be used to insure safe and proper power-up and power-down. the device ignores all instructions until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 5.3 . however, correct operation of the device is not guaranteed if v cc returns below v cc (min) during t pu . no command should be sent to the device until the end of t pu . after power-up (t pu ), the device is in standby mode (not deep power down mode), draws cmos standby current (i sb ), and the wel bit is reset. during power-down or voltage drops below v cc (cut-off), the voltag e must drop below v cc (low) for a period of t pd for the part to initialize correctly on power-up. see figure 5.4 . if during a voltage drop the v cc stays above v cc (cut-off) the part will stay initialized and will work correctly when v cc is again above v cc (min). in the event power-on reset (por) did not complete correctly after powe r up, the assertion of the reset# signal or receiving a software reset command (reset) will restart the por process. normal precautions must be taken for su pply rail decoupling to stabilize the v cc supply at the device. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package supply connection (this capacitor is gener ally of the order of 0.1 f). v il - 2.0v 20 ns 20 ns 20 ns v ih v io + 2.0v 20 ns 20 ns 20 ns
january 8, 2014 S25FL512S_00_07 S25FL512S 35 data sheet figure 5.3 power-up figure 5.4 power-down and voltage drop table 5.2 power-up / power-down voltage and timing symbol parameter min max unit v cc (min) v cc (minimum operation voltage) 2.7 v v cc (cut-off) v cc (cut 0ff where re-initialization is needed) 2.4 v v cc (low) v cc (low voltage for initialization to occur) v cc (low voltage for initialization to occur at embedded) 1.0 2.3 v t pu v cc (min) to read operation 300 s t pd v cc (low) time 1.0 s (max) (min) v cc t pu full device access time v cc v cc t pd (max) (min) v cc t pu device access allowed time v cc v cc no device access allowed (cut-off) v cc (low) v cc
36 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 5.4 dc characteristics applicable within operating ranges. notes: 1. typical values are at t ai = 25 c and v cc = v io = 3v. 2. output switching current is not included. 3. industrial temperature range / automotive in-cabin temperature range. 5.4.1 active power and standby power modes the device is enabled and in the active power mode when chip select (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, er ase, and write operations have completed. the device then goes into the stand by power mode, and power consumption drops to i sb . table 5.3 dc characteristics symbol parameter test conditions min typ (1) max unit v il input low voltage -0.5 0.2 x v io v v ih input high voltage 0.7 x v io v io +0.4 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min 0.15 x v io v v oh output high voltage i oh = ?0.1 ma 0.85 x v io v i li input leakage current v cc = v cc max, v in = v ih or v il 2 a i lo output leakage current v cc = v cc max, v in = v ih or v il 2 a i cc1 active power supply current (read) serial sdr@50 mhz serial sdr@133 mhz quad sdr @ 80 mhz quad sdr @104 mhz quad ddr @ 66 mhz quad ddr @80 mhz outputs unconnected during read data return (2) 16 33/35 (3) 50 61 75 90 ma i cc2 active power supply current (page program) cs# = v io 100 ma i cc3 active power supply current (wrr) cs# = v io 100 ma i cc4 active power supply current (se) cs# = v io 100 ma i cc5 active power supply current (be) cs# = v io 100 ma i sb (industrial) standby current reset#, cs# = v io ; si, sck = v io or v ss , industrial temp 70 100 a i sb (automotive) standby current reset#, cs# = v io ; si, sck = v io or v ss , automotive temp 70 300 a
january 8, 2014 S25FL512S_00_07 S25FL512S 37 data sheet 6. timing specifications 6.1 key to switching waveforms figure 6.1 waveform element meanings figure 6.2 input, output, and timing reference levels 6.2 ac test conditions figure 6.3 test setup input symbol output valid at logic high or low high impedance any change permitted logic high logic low changing, state unknown valid at logic high or low high impedance logic high logic low v io + 0.4v 0.7 x v io 0.2 x v io - 0.5v timing reference level 0.5 x v io 0.85 x v io 0.15 x v io input levels output levels device under test c l
38 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet notes: 1. output high-z is defined as the point where data is no longer driven. 2. input slew rate: 1.5 v/ns. 3. ac characteristics tables assume clock and data signals have the same slew rate (slope). 4. ddr operation. 6.2.1 capacitance characteristics note: 1. for more information on capacitanc e, please consult the ibis models. 6.3 reset 6.3.1 power-on (cold) reset the device executes a power-on reset (por) process until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 5.3 on page 35 , table 5.2 on page 35 , and table 6.3 on page 40 . the device must not be selected (cs# to go high with v io ) during power-up (t pu ), i.e. no commands may be sent to the device until the end of t pu . reset# is ignored du ring por. if reset# is low during por and remains low through and beyond the end of t pu , cs# must remain high until t rh after reset# returns high. reset# must return high for greater than t rs before returning low to initiate a hardware reset. figure 6.4 reset low at the end of por table 6.1 ac measurement conditions symbol parameter min max unit c l load capacitance 30 15 (4) pf input rise and fall times 2.4 ns input pulse voltage 0.2 x v io to 0.8 v io v input timing ref voltage 0.5 v io v output timing ref voltage 0.5 v io v table 6.2 capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#, reset#) 1 mhz 8 pf c out output capacitance (applies to all i/o) 1 mhz 8 pf vcc vio reset# cs# if reset# is low at tpu end cs# must be high at tpu end tpu trh
january 8, 2014 S25FL512S_00_07 S25FL512S 39 data sheet figure 6.5 reset high at the end of por figure 6.6 por followed by hardware reset 6.3.2 hardware (warm) reset when the reset# input transitions from v ih to v il the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is performed during por. the hardware reset process requires a period of t rph to complete. if the por process di d not complete correctly for any reason during power-up (t pu ), reset# going low will initiate the fu ll por process instead of the hardware reset process and will require t pu to complete the por process. the reset# input provides a hardware method of resetting the flash memory device to standby state. ? reset# must be high for t rs following t pu or t rph , before going low again to initiate a hardware reset. ? when reset# is driven low for at l east a minimum period of time (t rp ), the device terminates any operation in progress, tri-states all outputs, and ignores all read/write commands for the duration of t rph . the device resets the in terface to standby state. ? if cs# is low at the time reset# is asserted, cs# must return high during t rph before it can be asserted low again after t rh . ? hardware reset is only offered in 16-lead soic and bga packages. vcc vio reset# cs# if reset# is high at tpu end cs# may stay high or go low at tpu end tpu tpu vcc vio reset# cs# trs tpu tpu
40 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 6.7 hardware reset notes: 1. reset# low is optional and ignored during power-up (t pu ). if reset# is asserted during the end of t pu , the device will remain in the reset state and t rh will determine when cs# may go low. 2. sum of t rp and t rh must be equal to or greater than t rph. table 6.3 hardware reset parameters parameter description limit time unit t rs reset setup - prior reset end and reset# high before reset# low min 50 ns t rph reset pulse hold - reset# low to cs# low min 35 s t rp reset# pulse width min 200 ns t rh reset hold - reset# high before cs# low min 50 ns reset# cs# any prior reset trs trp trh trh trph trph
january 8, 2014 S25FL512S_00_07 S25FL512S 41 data sheet 6.4 sdr ac characteristics notes: 1. only applicable as a constraint for wrr instruction when srwd is set to a 1. 2. full v cc range (2.7 - 3.6v) and cl = 30 pf. 3. regulated v cc range (3.0 - 3.6v) and cl = 30 pf. 4. regulated v cc range (3.0 - 3.6v) and cl = 15 pf. 5. 10% duty cycle is supported for frequencies 50 mhz. 6. maximum value only applies during program/erase suspend/resume commands. 7. for automotive in-cabin temperature range (-40c to +105c), all sck frequencies are 5% slower than the max values shown. table 6.4 ac characteristics (single die package, v io = v cc 2.7v to 3.6v) symbol parameter min typ max unit f sck, r sck clock frequency for read and 4read instructions dc 50 (7) mhz f sck, c sck clock frequency for single commands as shown in table 10.2 on page 74 (4) dc 133 (7) mhz f sck, c sck clock frequency for the following dual and quad commands: dor, 4dor, qor, 4qor, dior, 4dior, qior, 4qior dc 104 (7) mhz f sck, qpp sck clock frequency for the qpp, 4qpp commands dc 80 (7) mhz p sck sck clock period 1/ f sck
42 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet notes: 1. only applicable as a constraint for wrr instruction when srwd is set to a 1. 2. cl = 30 pf. 3. cl = 15 pf. 4. 10% duty cycle is supported for frequencies 50 mhz. 5. maximum value only applies during program/erase suspend/resume commands. 6. for automotive in-cabin temperature range (-40c to +105c), all sck frequencies are 5% slower than the max values shown. 6.4.1 clock timing figure 6.8 clock timing table 6.5 ac characteristics (single die package, v io 1.65v to 2.7v, v cc 2.7v to 3.6v) symbol parameter min typ max unit f sck, r sck clock frequency for read, 4read instructions dc 50 (6) mhz f sck, c sck clock frequency for all others (3) dc 66 (6) mhz p sck sck clock period 1/ f sck
january 8, 2014 S25FL512S_00_07 S25FL512S 43 data sheet 6.4.2 input / output timing figure 6.9 spi single bit input timing figure 6.10 spi single bit output timing figure 6.11 spi sdr mio timing cs# sck si so msb in lsb in tcss tcss tcsh tcsh tcs tsu thd cs# sck si so msb out lsb out tcs tho tv tdis tlz cs# sck io msb in lsb in msb out . lsb out tcsh tcss tcss tsu thd tlz tho tcs tdis tv
44 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 6.12 hold timing figure 6.13 wp# input timing cs# sck hold# si_or_io_(during_input) so_or_io_(during_output) a b b c d e thz thz tlz tlz tchhl tchhl thlch thlch tchhh tchhh thhch hold condition standard use hold condition non-standard use cs# wp# sck si so phase 7654321076543210 wrr instruction input data twps twph
january 8, 2014 S25FL512S_00_07 S25FL512S 45 data sheet 6.5 ddr ac characteristics notes: 1. regulated v cc range (3.0 - 3.6v) and cl =15 pf. 2. maximum value only applies during program/erase suspend/resume commands. 3. for automotive in-cabin temperature range (-40c to +105c), all sck frequencies are 5% slower than the max values shown. table 6.6 ac characteristics ddr operation symbol parameter 66 mhz 80 mhz unit min typ max min typ max f sck, r sck clock frequency for ddr read instruction dc 66 (3) dc 80 (3) mhz p sck, r sck clock period for ddr read instruction 15 12.5 ns t wh , t ch clock high time 45% p sck 45% p sck ns t wl , t cl clock low time 45% p sck 45% p sck ns t cs cs# high time (read instructions) 10 10 ns t css cs# active setup time (relative to sck) 3 3 ns t csh cs# active hold time (relative to sck) 3 3 ns t su io in setup time 2 3000 (2) 1.5 3000 (2) ns t hd io in hold time 2 1.5 ns t v clock low to output valid 0 6.5 (1) 1.5 6.5 (1) ns t ho output hold time 0 1.5 ns t dis output disable time 8 8 ns t lz clock to output low impedance 0 8 0 8 ns t o_skew first output to last output data valid time 600 600 ps
46 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 6.5.1 ddr input timing figure 6.14 spi ddr input timing 6.5.2 ddr output timing figure 6.15 spi ddr output timing cs# sck si_or_io so msb in lsb in tcss tcss tcsh tcsh tcs tsu tsu thd thd cs# sck si so_or_io msb lsb tcs tho tv tv tdis tlz
january 8, 2014 S25FL512S_00_07 S25FL512S 47 data sheet figure 6.16 spi ddr data valid window notes: 1. t clh is the shorter duration of t cl or t ch . 2. t o_skew is the maximum difference (delta) between the minimum and maximum t v (output valid) across all io signals. 3. t ott is the maximum output transition time from one valid data value to the next valid data value on each io. 4. t ott is dependent on system level considerations including: a. memory device output impedance (drive strength). b. system level parasitics on the ios (primarily bus capacitance). c. host memory controller input v ih and v il levels at which 0 to 1 and 1 to 0 transitions are recognized. d. as an example, assuming that the above considerations result a memory output slew rate of 2v/ns and a 3v transition (from 1 t o 0 or 0 to 1) is required by the host, the t ott would be: t ott = 3v/(2v/ns) = 1.5 ns e. t ott is not a specification tested by spansio n, it is system dependent and must be derived by the system designer based on the abov e considerations. 5. the minimum data valid window (t dv ) can be calculated as follows: a. as an example, assuming: i. 80 mhz clock frequency = 12.5 ns clock period ii. ddr operations are specified to have a duty cycle of 45% or higher iii. t clh = 0.45*psck = 0.45x12.5 ns = 5.625 ns iv. t o_skew = 600 ps v. t ott = 1.5 ns b. t dv = t clh - t o_skew - t ott c. t dv = 5.625 ns - 600 ps - 1.5 ns = 3.525 ns io0 io1 io2 io_valid io3 tdv slow d1 slow d2 fast d1 fast d2 tv to_skew tv sck d1 valid tott tch tcl tdv d2 valid p sck
48 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 7. physical interface note: refer to table 3.1, signal list on page 16 for signal descriptions. 7.1 soic 16-lead package 7.1.1 soic 16 connection diagram figure 7.1 16-lead soic package, top view table 7.1 model specific connections vio / rfu versatile i/o or rfu - some device models bond this connector to the device i/o power supply, other models bond the device i/o supply to vcc within t he package leaving this package connector unconnected. reset# / rfu reset# or rfu - some device models bond this c onnector to the device reset# signal, other models bond the reset# signal to vcc within the package leaving this package connector unconnected. 1 2 3 4 16 15 14 13 hold#/io3 vcc reset#/rfu dnu nc vio/rfu si/io0 sck 5 6 7 8 12 11 10 9 wp#/io2 vss dnu dnu dnu rfu cs# so/io1
january 8, 2014 S25FL512S_00_07 S25FL512S 49 data sheet 7.1.2 soic 16 physical diagram s03016 ? 16-lead wide plastic small outline package (300-mil body width)
50 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 7.2 fab024 24-ball bga package 7.2.1 connection diagram figure 7.2 24-ball bga, 5 x 5 ball f ootprint (fab024), top view note: signal connections are in the same relative positions as fac 024 bga, allowing a single pcb footprint to use either package. 3 25 4 1 nc nc nc reset#/ rfu b d e a c vss sck nc vcc dnu rfu cs# nc wp#/io2 dnu si/io0 so/io1 nc hold#/io3 dnu nc nc nc vio/rfu nc
january 8, 2014 S25FL512S_00_07 S25FL512S 51 data sheet 7.2.2 fab024 physical diagram fab024 ? 24-ball bga (8 x 6 mm) package
52 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 7.3 fac024 24-ball bga package 7.3.1 connection diagram figure 7.3 24-ball bga, 4 x 6 ball footprint (fac024), top view note: 1. signal connections are in the same relative positions as fab024 bga, allowing a single pcb footprint to use either package. 3 24 1 nc nc reset#/ rfu b d e a c vss sck vcc dnu rfu cs# wp#/io2 dnu si/io0 so/io1 hold#/io3 dnu nc nc vio/rfu nc nc nc nc nc nc f
january 8, 2014 S25FL512S_00_07 S25FL512S 53 data sheet 7.3.2 fac024 physical diagram fac024 ? 24-ball bga (6 x 8 mm) package 7.3.3 special handling instru ctions for fbga packages flash memory devices in bga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. package fac024 jedec n/a d x e 8.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.20 profile a1 0.25 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 5.00 bsc. matrix footprint e1 3.00 bsc. matrix footprint md 6 matrix size d direction me 4 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter e 1.00 bsc. ball pitchl sd/ se 0.5/0.5 solder ball placement depopulated solder balls j package outline type 3642 f16-038.9 \ 09.10.09 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement.
54 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet software interface this section discusses the features and behaviors most re levant to host system software that interacts with the S25FL512S memory device. 8. address space maps 8.1 overview 8.1.1 extended address the S25FL512S device supports 32-bit addresses to enabl e higher density devices than allowed by previous generation (legacy) spi devices that supported only 24- bit addresses. a 24-bit byte resolution address can access only 16 mbytes (128 mbits) of maximum density. a 32-bit byte resolution address allows direct addressing of up to a 4 gbytes (32 gbits) of address space. legacy commands continue to support 24-bit addresses for backward software compatibility. extended 32-bit addresses are enabled in three ways: ? bank address register ? a software (command) loadable in ternal register that supplies the high order bits of address when legacy 24-bit addresses are in use. ? extended address mode ? a bank address register bit t hat changes all legacy commands to expect 32 bits of address supplied fr om the host system. ? new commands ? that perform both legacy and new functions, which expect 32-bit address. the default condition at power-up and after reset, is th e bank address register loaded with zeros and the extended address mode set for 24-bit addresses. this enabl es legacy software compatible access to the first 128 mbits of a device. 8.1.2 multiple address spaces many commands operate on the main flash memory array. some commands operate on address spaces separate from the main flash array. each separate address space uses the full 32-bit address but may only define a small portion of the available address space. 8.2 flash memory array the main flash array is divided into erase units called sectors. the sectors are organized as uniform 256-kbyte sectors. note : this is a condensed table that uses a sector as a reference. there are address ranges that are not explicitly listed. all 256-kb sect ors have the patt ern xxxx0000h-xxxxffffh. 8.3 id-cfi address space the rdidj command (9fh) reads information from a separate flash memory address space for device identification (id) and common flash interface (cfi) information. see device id and common flash interface (id-cfi) address map on page 122 for the tables defining the cont ents of the id-cfi address space. the id-cfi address space is programmed by spans ion and read-only for the host system. table 8.1 S25FL512S sector and memory address map, uniform 256-kbyte sectors sector size (kbyte) sector count sector range address range (8-bit) notes 256 256 sa00 00000000h-0003ffffh sector starting address ? sector ending address : : sa255 03fc0000h-03ffffffh
january 8, 2014 S25FL512S_00_07 S25FL512S 55 data sheet 8.4 jedec jesd216 serial flash disco verable parameters (sfdp) space. the rsfdp command (5ah) reads information from a separate flash memory address space for device identification, feature, and configuration information, in accord with the jedec jesd216 standard for serial flash discoverable parameters. the id-cfi address spac e is incorporated as one of the sfdp parameters. see section 11.2, serial flash discoverable para meters (sfdp) address map on page 120 for the table defining the contents of the sfdp address space. th e sfdp address space is programmed by spansion and is read-only for the host system 8.5 otp address space each S25FL512S memory device has a 1024-byte one ti me program (otp) address space that is separate from the main flash array. the otp area is divided in to 32, individually lockable, 32-byte aligned and length regions. in the 32-byte region starting at address zero: ? the 16 lowest address bytes are programmed by span sion with a 128-bit random number. only spansion is able to program these bytes. ? the next 4 higher address bytes (otp lock bytes) are used to provide one bit per otp region to permanently protect each region from programming. the bytes are er ased when shipped from spansion. after an otp region is programmed, it can be lock ed to prevent further programming, by programming the related protection bit in the otp lock bytes. ? the next higher 12 bytes of the lowest address region are reserved for future use (rfu). the bits in these rfu bytes may be programmed by the host system but it must be understood that a future device may use those bits for protection of a larger otp space. the bytes are erased when shipped from spansion. the remaining regions are erased when shipped from spansion, and are available for programming of additional permanent data. refer to figure 8.1, otp address space on page 56 for a pictorial representation of the otp memory space. the otp memory space is intended for increased system security. otp values, such as the random number programmed by spansion, can be used to ?mate? a fl ash component with the system cpu/asic to prevent device substitution. the configuration register freeze (cr1[0]) bit protects the entire otp memory space from programming when set to 1. this allows trusted boot code to c ontrol programming of otp regions then set the freeze bit to prevent further otp memory space programming during the rema inder of normal power-on system operation.
56 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 8.1 otp address space table 8.2 otp address map region byte address range (hex) contents initial delivery state (hex) region 0 000 least significant byte of spansion programmed random number spansion programmed random number ... ... 00f most significant byte of spansion programmed random number 010 to 013 region locking bits byte 10 [bit 0] locks region 0 from programming when = 0 ... byte 13 [bit 7] locks region 31 from programming when = 0 all bytes = ff 014 to 01f reserved for future use (rfu) all bytes = ff region 1 020 to 03f available for user programming all bytes = ff region 2 040 to 05f available for user programming all bytes = ff ... ... available for user programming all bytes = ff region 31 3e0 to 3ff available for user programming all bytes = ff 3 2 byte otp region 3 1 3 2 byte otp region 3 0 3 2 byte otp region 2 9 . . . 3 2 byte otp region 3 3 2 byte otp region 2 3 2 byte otp region 1 3 2 byte otp region 0 16 byte r a ndom numbe r reserve d lock byte s lock bit s3 1to 0 ... when progr a mmed to ?0? e a ch lock b it protect s it s rel ated 32 b yte region from any fu rther progra mming contents of region 0 { byte 0 byte 10 byte 1 f
january 8, 2014 S25FL512S_00_07 S25FL512S 57 data sheet 8.6 registers registers are small groups of memory cells used to configure how the s25fl512-s memory device operates or to report the status of device operations. t he registers are accessed by specific commands. the commands (and hexadecimal instruction codes) used for each register are noted in each register description. the individual register bits may be volatile, non-vol atile, or one time programmable (otp). the type for each bit is noted in each register description. the default state shown for each bit refers to the state after power-on reset, hardware rese t, or software reset if the bit is volatile. if the bit is non-volatile or otp, the default state is the value of the bit when the device is shipped from spansion. non-volatile bits have the same cycling (erase and program) endurance as the main flash array. 8.6.1 status register 1 (sr1) related commands: read status register (rdsr1 0 5h), write registers (wrr 01h), write enable (wren 06h), write disable (wrdi 04h), cle ar status register (clsr 30h). the status register contains both status and control bits: status register write disable (srwd) sr1[7] : places the device in the hardware protected mode when this bit is set to 1 and the wp# input is driven low. in this mode, the srwd, bp2, bp1, and bp0 bits of the status register become read-only bits and the write registers (wrr) command is no longer accepted for execution. if wp# is high the srwd bit and bp bits may be changed by the wrr command. if srwd is 0, wp# has no effect and the srwd bit and bp bits may be changed by the wrr command. the srwd bit has the same non-volatile endurance as the main flash array. program error (p_err) sr1[6] : the program error bit is used as a program operation success or failure indication. when the program error bit is set to a 1 it indicates that there was an error in the last program operation. this bit will also be set when the user attemp ts to program within a protected main memory sector or locked otp region. when the program error bit is set to a 1 this bit can be reset to 0 with the clear status register (clsr) command. this is a read-only bit and is not affected by the wrr command. erase error (e_err) sr1[5] : the erase error bit is used as an erase operation success or failure indication. when the erase error bit is set to a 1 it indica tes that there was an error in the last erase operation. this bit will also be set when the user attempts to erase an individual protected main memory sector. the bulk erase command will not set e_err if a protected sector is found during the command execution. when the erase error bit is set to a 1 this bit can be reset to 0 with the clear status r egister (clsr) command. this is a read-only bit and is not affected by the wrr command. table 8.3 status register-1 (sr1) bits field name function type default state description 7 srwd status register write disable non-volatile 0 1 = locks state of srwd, bp, and configuration register bits when wp# is low by ignoring wrr command 0 = no protection, even when wp# is low 6 p_err programming error occurred volatile, read only 0 1 = error occurred. 0 = no error 5 e_err erase error occurred volatile, read only 0 1 = error occurred 0 = no error 4 bp2 block protection volatile if cr1[3]=1, non-volatile if cr1[3]=0 1 if cr1[3]=1, 0 when shipped from spansion protects selected range of sectors (block) from program or erase 3 bp1 2 bp0 1 wel write enable latch volatile 0 1 = device accepts write registers (wrr), program or erase commands 0 = device ignores write registers (wrr), program or erase commands this bit is not affected by wrr, only wren and wrdi commands affect this bit 0 wip write in progress volatile, read only 0 1 = device busy, a write registers (wrr), program, erase or other operation is in progress 0 = ready device is in standby mode and can accept commands
58 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet block protection (bp2, bp1, bp0) sr1[4:2] : these bits define the main flash array area to be software- protected against program and erase co mmands. the bp bits are either volat ile or non-volatile, depending on the state of the bp non-volatile bit (bpnv) in the configur ation register. when one or more of the bp bits is set to 1, the relevant memory area is protected agains t program and erase. the bu lk erase (be) command can be executed only when the bp bits are cleared to 0?s. see block protection on page 66 for a description of how the bp bit values select the memory array area protected. the bp bits have the same non-volatile endurance as the main flash array. write enable latch (wel) sr1[1] : the wel bit must be set to 1 to enable program, write, or erase operations as a means to provide protection against inadv ertent changes to memory or register values. the write enable (wren) command execution sets the write enable latch to a 1 to allow any program, erase, or write commands to execute afterw ards. the write disable (wrdi) co mmand can be used to set the write enable latch to a 0 to prevent all program, erase, and write commands from execution. the wel bit is cleared to 0 at the end of any successful program, writ e, or erase operation. following a failed operation the wel bit may remain set and should be cleared with a wrdi command following a clsr command. after a power down/power up sequence, hardware reset, or softwa re reset, the write enable latch is set to a 0 the wrr command does not affect this bit. write in progress (wip) sr1[0] : indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the bit is set to a 1 the device is busy performing an operation. wh ile wip is 1, only read status (rdsr1 or rdsr2), erase suspend (ersp), program suspend (pgsp), clear status register (clsr), and software reset (reset) commands may be accepted. ersp and pgsp will only be accepted if memory array erase or program operations are in progress. the status register e_err and p_ err bits are updated while wip = 1. when p_err or e_err bits are set to one, the wip bit will remain set to one indicating the device remains busy and unable to receive new operation commands. a clear status register (clsr) command must be received to return the device to standby mode. when the wip bit is cleared to 0 no operation is in progress. this is a read-only bit. 8.6.2 configuration register 1 (cr1) related commands: read configuration register (rdcr 35h), write registers (wrr 01h). the configuration register bits can be changed us ing the wrr command with sixteen input cycles. the configuration register c ontrols certain interface a nd data protection functions. table 8.4 configuration register (cr1) bits field name function type default state description 7 lc1 latency code non-volatile 0 selects number of initial read latency cycles see latency code tables 6 lc0 0 5 tbprot configures start of block protection otp 0 1 = bp starts at bottom (low address) 0 = bp starts at top (high address) 4 rfu rfu rfu 0 reserved for future use 3 bpnv configures bp2-0 in status register otp 0 1 = volatile 0 = non-volatile 2 rfu rfu rfu 0 reserved for future use 1 quad puts the device into quad i/o operation non-volatile 0 1 = quad 0 = dual or serial 0 freeze lock current state of bp2-0 bits in status register, tbprot in configuration register, and otp regions volatile 0 1 = block protection and otp locked 0 = block protection and otp un-locked
january 8, 2014 S25FL512S_00_07 S25FL512S 59 data sheet latency code (lc) cr1[7:6]: the latency code selects the number of mode and dummy cycles between the end of address and the start of re ad data output for all read commands. some read commands send mode bits following the addre ss to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. the next command thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can be returned to the host system. some read commands require additional latency cycles as the sck frequency is increased. the following latency code tables provide different latency settings that are conf igured by spansion. the high performance versus the enhanced high performance se ttings are selected by the ordering part number. where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported at the frequency shown. r ead is supported only up to 50 mhz but the same latency value is assigned in each latency code and the command may be used when the device is operated at 50 mhz with any latency code setting. similarly, only the fast read command is supported up to 133 mhz but the same 10b latency code is used for fast read up to 133 mhz and for the other dual and quad read commands up to 104 mhz. it is not necessary to change the latency code from a higher to a lower frequency when operating at lower frequencies where a particular command is suppor ted. the latency code values for a higher frequency can be used for accesses at lower frequencies. the high performance settings provide latency options that are the same or faster than alternate source spi memories. these settings provide mode bits only for the quad i/o read command. the enhanced high performance settings similarly provide latency options the same or faster than additional alternate source spi memories and adds mode bits for the dual i/o read, ddr fast read, and ddr dual i/o read commands. read ddr data learning pattern (dlp) bits may be plac ed within the dummy cycles immediately before the start of read data, if there ar e 5 or more dummy cycles. see read memory array commands on page 89 for more information on the dlp. table 8.5 latency codes for sdr high performance freq. (mhz) lc read fast read read dual out read quad out dual i/o read quad i/o read (03h, 13h) (0bh, 0ch) (3bh, 3ch) (6bh, 6ch) (bbh, bch) (ebh, ech) mode dummy mode dummy mode dummy mode dummy mode dummy mode dummy 5011000000000421 8000- - 0808080424 9001- - 0808080524 10410- - 0808080625 1 3 31 0--08-------- table 8.6 latency codes for ddr high performance freq. (mhz) lc ddr fast read ddr dual i/o read read ddr quad i/o (0dh, 0eh) (bdh, beh) (edh, eeh) mode dummy mode dummy mode dummy 5 01 1040413 6 60 0050616 6 60 1060717 6 61 0070818
60 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet top or bottom protect ion (tbprot) cr1[5]: this bit defines the operation of the block protection bits bp2, bp1, and bp0 in the status register. as described in the status register section, the bp2-0 bits allow the user to optionally protect a portion of the array, r anging from 1/64, 1/4, 1/2, etc., up to the entire array. when tbprot is set to a 0 the block protection is defined to start from the top (maximum address) of the array. when tbprot is set to a 1 the block protection is defined to star t from the bottom (zero address) of the array. the tbprot bit is otp and set to a 0 when shipped from spansion. if tbprot is programmed to 1, an attempt to change it back to 0 will fail an d set the program error bit (p_err in sr1[6]). the desired state of tbprot must be selected during the initial configuratio n of the device during system manufacture; before the first program or erase operation on the main flash array. tbprot must not be programmed after programming or erasing is done in the main flash array. cr1[4]: reserved for future use block protection non-volatile (bpnv) cr1[3] : the bpnv bit defines whether or not the bp2-0 bits in the status register are volatile or non-volatile. the bpnv bi t is otp and cleared to a0 with the bp bits cleared to 000 when shipped from spansion. when bpnv is set to a 0 the bp2-0 bits in the status register are non- volatile. when bpnv is set to a 1 the bp2-0 bits in the status register are volatile and will be reset to binary 111 after por, hardware reset, or command reset. if bpnv is programmed to 1, an attempt to change it back to 0 will fail and set the program error bit (p_err in sr1[6]). cr1[2] : reserved for future use. quad data width (quad) cr1[1] : when set to 1, this bit switches th e data width of the device to 4 bit - quad mode. that is, wp# becomes io2 and hold# be comes io3. the wp# and hold# inputs are not monitored for their normal functions and are internally set to high (inactive). the commands for serial, dual output, and dual i/o read still function normally but, th ere is no need to drive wp# and hold# inputs for those commands when switching between commands usi ng different data path widths. the quad bit must be set to one when using read quad out, quad i/o read, read ddr quad i/o, and quad page program commands. the quad bit is non-volatile. freeze protection (freeze) cr1[0] : the freeze bit, when set to 1, locks the current state of the bp2-0 bits in status register, the tbprot and tbparm bits in the configurat ion register, and the otp address space. this prevents writing, progr amming, or erasing these areas. as long as the freeze bit remains cleared to logic 0 the other bits of the configuratio n register, including freeze, are writable, and the otp address space is programmable. once the freeze bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-on cycle or a hardware reset. software reset will not affect the state of the freeze bit. the freeze bit is volatile and the defa ult state of freeze after pow er-on is 0. the freeze bit can be set in parallel with updating other values in cr1 by a single wrr command. table 8.7 latency codes for sdr enhanced high performance freq. (mhz) lc read fast read read dual out read quad out dual i/o read quad i/o read (03h, 13h) (0bh, 0ch) (3bh, 3ch) (6bh, 6ch) (bbh, bch) (ebh, ech) mode dummy mode dummy mode dummy mode dummy mode dummy mode dummy 5011000000004021 8000- - 0808084024 9001- - 0808084124 10410- - 0808084225 13310--08-------- table 8.8 latency codes for ddr enhanced high performance freq. (mhz) lc ddr fast read ddr dual i/o read read ddr quad i/o (0dh, 0eh) (bdh, beh) (edh, eeh) mode dummy mode dummy mode dummy 5 01 1412213 6 60 0422416 6 60 1442517 6 61 0452618
january 8, 2014 S25FL512S_00_07 S25FL512S 61 data sheet 8.6.3 status register 2 (sr2) related commands: read status register 2 (rdsr2 07h). erase suspend (es) sr2[1] : the erase suspend bit is used to determine when the device is in erase suspend mode. this is a status bit that cannot be writte n. when erase suspend bit is set to 1, the device is in erase suspend mode. when erase suspend bit is cleared to 0, the device is not in erase suspend mode. refer to erase suspend and resume commands (75h) (7ah) for details about the erase suspend/resume commands. program suspend (ps) sr2[0]: the program suspend bit is used to determine when the device is in program suspend mode. this is a status bit that cannot be written. when pr ogram suspend bit is set to 1, the device is in program suspend mode. when the program suspend bit is cleared to 0, the device is not in program suspend mode. refer to program suspend (pgsp 85h) and resume (pgrs 8ah) on page 106 for details. 8.6.4 autoboot register related commands: autoboot read (ab rd 14h) and autoboot write (abwr 15h). the autoboot register provides a me ans to automatically read boot code as part of the power on reset, hardware reset, or so ftware reset process. table 8.9 status register-2 (sr2) bits field name function type default state description 7 rfu reserved 0 reserved for future use 6 rfu reserved 0 reserved for future use 5 rfu reserved 0 reserved for future use 4 rfu reserved 0 reserved for future use 3 rfu reserved 0 reserved for future use 2 rfu reserved 0 reserved for future use 1 es erase suspend volatile, read only 0 1 = in erase suspend mode 0 = not in erase suspend mode 0 ps program suspend volatile, read only 0 1 = in program suspend mode 0 = not in program suspend mode
62 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 8.6.5 bank address register related commands: bank register access (brac b9h) , write register (wrr 01h), bank register read (brrd 16h) and bank register write (brwr 17h). the bank address register supplies additional high or der bits of the main flash array byte boundary address for legacy commands that supply only the low order 24 bits of address. the bank address is used as the high bits of address (above a23) for all 3-byte address commands when extadd=0. the bank address is not used when extadd = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address. extended address (extadd) bar[7]: extadd controls th e address field size for legacy spi commands. by default (power up reset, hardware reset, and software reset) , it is cleared to 0 for 3 bytes (24 bits) of address. when set to 1, the legacy commands will require 4 bytes (32 bits) for the address field. this is a volatile bit. table 8.10 autoboot register bits field name function type default state description 31 to 9 absa autoboot start address non-volatile 000000h 512 byte boundary address for the start of boot code access 8 to 1 absd autoboot start delay non-volatile 00h number of initial delay cycles between cs# going low and the first bit of boot code being transferred 0 abe autoboot enable non-volatile 0 1 = autoboot is enabled 0 = autoboot is not enabled table 8.11 bank address register (bar) bits field name function type default state description 7 extadd extended address enable volatile 0b 1 = 4-byte (32-bits) addressing required from command. 0 = 3-byte (24-bits) addressing from command + bank address 6 to 2 rfu reserved volatile 00000b reserved for future use 1 ba25 bank address volatile 0 a25 for 512 mb device 0 rfu bank address volatile 0 rfu for lower density device
january 8, 2014 S25FL512S_00_07 S25FL512S 63 data sheet 8.6.6 asp regi ster (aspr) related commands: asp read (asprd 2bh) and asp program (aspp 2fh). the asp register is a 16-bit otp memory location used to permanently configure the behavior of advanced sector protection (asp) features. note: 1. default value depends on ordering part number, see initial delivery state on page 136 . reserved for future us e (rfu) aspr[15:3, 0] . password protection mode lo ck bit (pwdmlb) aspr[2]: when programmed to 0, the password protection mode is pe rmanently selected. persistent protection mode lock bit (pstmlb) aspr[1]: when programmed to 0, the persistent protection mode is permanently se lected. pwdmlb and pstmlb are mu tually exclusive, only one may be programmed to zero. 8.6.7 password register (pass) related commands: password read (passrd e7h) and password program (passp e8h). 8.6.8 ppb lock register (ppbl) related commands: ppb lock read (plbrd a7h, plbwr a6h) table 8.12 asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use 8 rfu reserved otp (note 1) reserved for future use 7 rfu reserved otp (note 1) reserved for future use 6 rfu reserved otp 1 reserved for future use 5 rfu reserved otp (note 1) reserved for future use 4 rfu reserved otp (note 1) reserved for future use 3 rfu reserved otp (note 1) reserved for future use 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protection mode permanently enabled. 1 = persistent protection mode not permanently enabled. 0 rfu reserved otp 1 reserved for future use table 8.13 password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff- ffffffffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to zero. table 8.14 ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile persistent protection mode = 1 password protection mode = 0 0 = ppb array protected until next power cycle or hardware reset 1 = ppb array may be programmed or erased.
64 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 8.6.9 ppb access register (ppbar) related commands: ppb read (ppbrd e2h) 8.6.10 dyb access register (dybar) related commands: dyb read (dybrd e0h) and dyb program (dybp e1h). 8.6.11 spi ddr data learning registers related commands: program nvdlr (pnvdlr 43h), write vdlr (wvdlr 4ah), data learning pattern read (dlprd 41h). the data learning pattern (dlp) resides in an 8-bit non-volatile data learning register (nvdlr) as well as an 8-bit volatile data learning register (vdlr). when shipped from spansion, the nvdlr value is 00h. once programmed, the nvdlr cannot be reprogrammed or erased; a copy of the data pattern in the nvdlr will also be written to the vdlr. the vdlr can be writt en to at any time, but on reset or power cycles the data pattern will revert back to what is in the nvdl r. during the learning phase described in the spi ddr modes, the dlp will come from the vdlr. each io will output the same dlp value for every clock edge. for example, if the dlp is 34h (or binary 00110100) t hen during the first clock edge all io?s will output 0; subsequently, the 2nd clock edge all i/o?s will output 0, the 3r d will output 1, etc. when the vdlr value is 00h, no preamble data pattern is presented during the dummy phase in the ddr commands. table 8.15 ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to 0, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd or ppbp command is erased to 1, not protecting that sector from program or erase operations. table 8.16 dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybp command is cleared to 0, protecting that sector from program or erase operations. ffh = dyb for the sector addressed by the dybrd or dybp command is set to 1, not protecting that sector from program or erase operations. table 8.17 non-volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 nvdlp non-volatile data learning pattern otp 00h otp value that may be transferred to the host during ddr read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. table 8.18 volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 vdlp volatile data learning pattern volatile takes the value of nvdlr during por or reset volatile copy of the nvdlp used to enable and deliver the data learning pattern (dlp) to the outputs. the vdlp may be changed by the host during system operation.
january 8, 2014 S25FL512S_00_07 S25FL512S 65 data sheet 9. data protection 9.1 secure silicon region (otp) the device has a 1024-byte one time program (otp) address space that is separate from the main flash array. the otp area is divided into 32, individual ly lockable, 32-byte aligned and length regions. the otp memory space is intended for increased system security. otp values can ?mate? a flash component with the system cpu/asic to prevent device substitution. see otp address space on page 55 , one time program array commands on page 111 , and otp read (otpr 4bh): on page 111 . 9.1.1 reading otp memory space the otp read command uses the same protocol as fa st read. otp read operations outside the valid 1-kb otp address range will yield indeterminate data. 9.1.2 programming otp memory space the protocol of the otp programmi ng command is the same as page program. the otp program command can be issued multiple times to any given otp address, but this address space can never be erased. the valid address range for otp program is depicted in figure 8.1, otp address space on page 56 . otp program operations outside the valid otp address range will be ignored and the wel in sr1 will remain high (set to 1). otp program operations while freeze = 1 will fail with p_err in sr1 set to 1. 9.1.3 spansion prog rammed random number spansion standard practice is to progr am the low order 16 bytes of the ot p memory space (locations 0x0 to 0xf) with a 128-bit random number using the linear co ngruential random number method. the seed value for the algorithm is a random number concatenate d with the day and time of tester insertion. 9.1.4 lock bytes the lsb of each lock byte protects the lowest addres s region related to the byte, the msb protects the highest address region related to the byte. the next hig her address byte similarly protects the next higher 8 regions. the lsb bit of the lowest address lock byte protects the higher address 16 bytes of the lowest address region. in other words, the lsb of location 0x 10 protects all the lock bytes and rfu bytes in the lowest address region from further programming. see section 8.5, otp address space on page 55 . 9.2 write enable command the write enable (wren) command must be written prio r to any command that modifies non-volatile data. the wren command sets the write enable latch (wel) bit. the wel bit is cleared to 0 (disables writes) during power-up, hardware reset, or after the device completes the following commands: ? reset ? page program (pp) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write registers (wrr) ? quad-input page programming (qpp) ? otp byte programming (otpp)
66 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 9.3 block protection the block protect bits (status register bits bp2, bp1 , bp0) in combination with the configuration register tbprot bit can be used to protect an address range of the main flash array from program and erase operations. the size of the range is determined by the value of the bp bits and the upper or lower starting point of the range is selected by the t bprot bit of the configuration register. when block protection is enabled (i.e ., any bp2-0 are set to 1), advanced sector protection (asp) can still be used to protect sectors not protected by the block pr otection scheme. in the case that both asp and block protection are used on the same sector the logical or of asp and block protection related to the sector is used. recommendation: asp a nd block protection should not be used concurrently. use one or the other, but not both. 9.3.1 freeze bit bit0 of the configuration r egister is the freeze bit. the freeze bit locks the bp2-0 bits in status register 1 and the tbprot bit in the configuration register to th eir value at the time the freeze bit is set to 1. once the freeze bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is executed. as long as the freeze bit is cleared to logi c 0 the status register bp bits and the tbprot bit of the configuration register are writ able. the freeze bit also protects the entire otp memory space from programming when set to 1. any attempt to change t he bp bits with the wrr command while freeze = 1 is ignored and no error status is set. 9.3.2 write protect signal the write protect (wp#) input in combination with the status register write disable (srwd) bit provide hardware input signal controlled protection. when wp# is low and srwd is set to 1 the status and configuration register is protected fr om alteration. this prev ents disabling or changing the protection defined by the block protect bits. table 9.1 upper array start of protection (tbprot = 0) status register content protected fraction of memory array protected memory (kbytes) fl512s 512 mb bp2 bp1 bp0 000 none 0 0 0 1 upper 64th 1024 0 1 0 upper 32nd 2048 0 1 1 upper 16th 4096 1 0 0 upper 8th 8192 1 0 1 upper 4th 16384 1 1 0 upper half 32768 1 1 1 all sectors 65536 table 9.2 lower array start of protection (tbprot = 1) status register content protected fraction of memory array protected memory (kbytes) fl512s 512 mb bp2 bp1 bp0 000 none 0 0 0 1 lower 64th 1024 0 1 0 lower 32nd 2048 0 1 1 lower 16th 4096 1 0 0 lower 8th 8192 1 0 1 lower 4th 16384 1 1 0 lower half 32768 1 1 1 all sectors 65536
january 8, 2014 S25FL512S_00_07 S25FL512S 67 data sheet 9.4 advanced sector protection advanced sector protection (asp) is the name used for a set of independent hardware and software methods used to disable or enable programming or erase operations, individually, in any or all sectors. an overview of these methods is shown in figure 9.1, advanced sector protection overview on page 67 . block protection and asp protection settings for each sect or are logically or?d to define the pr otection for each sector, i.e. if either mechanism is protecting a sector the sect or cannot be programmed or erased. refer to block protection on page 66 for full details of the bp2-0 bits. figure 9.1 advanced sector protection overview every main flash array sector has a non-volatile (ppb) and a volatile (dyb) protection bit associated with it. when either bit is 0, the sector is prot ected from program an d erase operations. the ppb bits are protected from program and erase when the ppb lock bit is 0. there are two methods for managing the state of the ppb lock bit, persis tent protection and password protection. the persistent protection method sets the ppb lock bit to 1 during por, or hardwa re reset so that the ppb bits are unprotected by a device reset. there is a co mmand to clear the ppb lock bi t to 0 to protect the ppb. there is no command in the persistent protection method to set the ppb lock bit to 1, therefore the ppb lock bit will remain at 0 until the next power-off or ha rdware reset. the persistent protection method allows boot code the option of chang ing sector protection by programming or erasing th e ppb, then pr otecting the ppb from further change for the remainder of normal syst em operation by clearing the ppb lock bit to 0. this is sometimes called boot-code controlled sector protection. the password method clears the ppb lock bit to 0 durin g por, or hardware reset to protect the ppb. a 64-bit password may be permanently programmed and hidden for the password method. a command can be used to provide a password for comparison with the hidden password. if the password matches, the ppb lock bit is set to 1 to unprotect the ppb. a command c an be used to clear the ppb lock bit to 0. this method requires use of a password to control ppb protection. a s p regi s ter one time progr a mmable p ass word method ( a s pr[2]=0) per s i s tent method ( a s pr[1]=0) 64 - b it p assword (one time protect) pbb lock bit ? 0 ? = ppb s locked s ector 0 memory arr a y s ector n - 2 s ector 1 s ector 2 s ector n - 1 s ector n 1.) n = highe s t addre ss s ector ppb 0 per s i s tent protection bit (ppb) ppb n - 2 ppb 1 ppb 2 ppb n - 1 ppb n dyb 0 dyn a mic protection bit (dyb) dyb n - 2 dyb 1 dyb 2 dyb n - 1 dyb n 2.) 3 .) dyb a re vol a tile b it s ? 1 ? =ppb s u nlocked 64 - b it p assword (one time protect) s ector 0 memory arr a y s ector n - 2 s ector 1 s ector 2 s ector n - 1 s ector n 1.) n = highe s t addre ss s ector, a s ector i s protected if it s ppb = ? 0 ? or it s dyb = ? 0 ? ppb 0 per s i s tent protection bit s (ppb) ppb n - 2 ppb 1 ppb 2 ppb n - 1 ppb n dyb 0 dyn a mic protection bit s (dyb) dyb n - 2 dyb 1 dyb 2 dyb n - 1 dyb n ppb a re progr a mmed individ ua lly but er as ed as a gro u p 3 .) dyb a re vol a tile b it s 4.) ppb lock b it i s vol a tile a nd def aults to ? 1 ? (per sis tent mode).or ? 0 ? (p ass word mode) u pon re s et 5.) ppb lock = ? 0 ? lock s a ll ppb s to their c u rrent s ta te 6.) p ass word method re qu ire s a p ass word to s et ppb lock to ? 1 ? to en ab le progr a m or er as e of ppb b its 7.) per sis tent method only a llow s ppb lock to b e cle a red to ? 0 ? to prevent progr a m or er as e of ppb b its . power off or h a rdw a re re s et re qu ired to s et ppb lock to ? 1 ?
68 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet the selection of the ppb lock bit management met hod is made by programming otp bits in the asp register so as to permanently select the method used. 9.4.1 asp register the asp register is used to permanently configur e the behavior of advanced sector protection (asp) features. see table 8.12, asp register (aspr) on page 63 . as shipped from the factory, all dev ices default asp to the persistent protection mode, with all sectors unprotected, when power is applied. the device program mer or host system must then choose which sector protection method to use. progra mming either of the, one-time programmable, protection mode lock bits, locks the part permanently in the selected mode: ? aspr[2:1] = 11 = no asp mode selected, persistent protection mode is the default. ? aspr[2:1] = 10 = persistent prot ection mode permanently selected. ? aspr[2:1] = 01 = password protec tion mode permanently selected. ? aspr[2:1] = 00 = ill egal condition, attempting to program both bits to zero resu lts in a programming failure. asp register prog ramming rules: ? if the password mode is chosen, the password must be programmed prior to setting the protection mode lock bits. ? once the protection mode is selected, the protec tion mode lock bits are permanently protected from programming and no further changes to the asp register is allowed. the programming time of the asp register is the same as the typical page pr ogramming time. the system can determine the status of the asp register programming operation by reading the wip bit in the status register. see status register 1 (sr1) on page 57 for information on wip. after selecting a sector protection method, each se ctor can operate in each of the following states: ? dynamically locked ? a sector is protect ed and can be changed by a simple command. ? persistently locked ? a sector is protected and cannot be changed if its ppb bit is 0. ? unlocked ? the sector is unprotected and can be changed by a simple command. 9.4.2 persistent protection bits the persistent protecti on bits (ppb) are located in a separate nonvolatile flash a rray. one of the ppb bits is related to each sector. when a ppb is 0, its related se ctor is protected from pr ogram and erase operations. the ppb are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time. the ppb have the same program and erase endurance as the main flash me mory array. preprogramming and verification prior to erasure are handled by the device. programming a ppb bit requires the typical page progra mming time. erasing all the ppbs requires typical sector erase time. during ppb bit pr ogramming and ppb bit erasing, status is available by reading the status register. reading of a ppb bit requires th e initial access time of the device. notes: 1. each ppb is individually programmed to 0 and all are erased to 1 in parallel. 2. if the ppb lock bit is 0, the ppb program or ppb erase command does not execute and fails without programming or erasing the ppb. 3. the state of the ppb for a given sector can be verified by using the ppb read command. 9.4.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dyb only control the protection for sectors t hat have their ppb set to 1. by issu ing the dyb write command, a dyb is cleared to 0 or set to 1, thus placing each sector in the protected or unprotecte d state respectively. this feature allows software to easily protect sectors agai nst inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. the dybs can be set or cleared as often as needed as they are volatile bits.
january 8, 2014 S25FL512S_00_07 S25FL512S 69 data sheet 9.4.4 ppb lock bit (ppbl[0]) the ppb lock bit is a volatile bit for protecting all ppb bits. when cleared to 0, it locks all ppbs and when set to 1, it allows th e ppbs to be changed. the plbwr command is used to cl ear the ppb lock bit to 0. the ppb lo ck bit must be cl eared to 0 only after all the ppbs are configured to the desired settings. in persistent protection m ode, the ppb lock is set to 1 during por or a hardware reset. when cleared to 0, no software command sequence can set the ppb lock bit to 1, only another hardware reset or power-up can set the ppb lock bit. in the password protection m ode, the ppb lock bit is clea red to 0 during por or a hardware reset. the ppb lock bit can only be set to 1 by the password unlock command. 9.4.5 sector protection states summary each sector can be in one of the following protection states: ? unlocked ? the sector is unprot ected and protection can be changed by a simple command. the protection state defaults to un protected after a power cycle, software reset, or hardware reset. ? dynamically locked ? a sector is protected and pr otection can be changed by a simple command. the protection state is not saved across a power cycle or reset. ? persistently locked ? a sector is protected and protection can only be changed if the ppb lock bit is set to 1. the protection state is non-volat ile and saved across a power cycle or reset. changi ng the protection state requires programming and or erase of the ppb bits 9.4.6 persistent protection mode the persistent protection method sets the ppb lock bit to 1 during por or hardware re set so that the ppb bits are unprotected by a device hardware reset. so ftware reset does not affect the ppb lock bit. the plbwr command can clear the ppb lock bit to 0 to protect the ppb. th ere is no command to set the ppb lock bit therefore the ppb lock bit will remain at 0 until the next power-off or hardware reset. 9.4.7 password protection mode password protection mode allows an even higher level of security than the pers istent sector protection mode, by requiring a 64-bit password for unlocking the ppb lock bit. in addition to this password requirement, after power up and hardware reset, the ppb lock bit is cl eared to 0 to ensure protection at power-up. successful execution of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppb modifications. password protection notes: ? once the password is programmed and verified, the pa ssword mode (aspr[2]=0) mu st be set in order to prevent reading the password. ? the password program command is only capable of programming ?0?s. programming a 1 after a cell is programmed as a 0 results in the cell left as a 0 with no programming error set. table 9.3 sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected ? ppb and dyb are changeable 1 1 0 protected ? ppb and dyb are changeable 1 0 1 protected ? ppb and dyb are changeable 1 0 0 protected ? ppb and dyb are changeable 0 1 1 unprotected ? ppb not changeable, dyb is changeable 0 1 0 protected ? ppb not changeable, dyb is changeable 0 0 1 protected ? ppb not changeable, dyb is changeable 0 0 0 protected ? ppb not changeable, dyb is changeable
70 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet ? the password is all 1?s when shipped from spansion. it is located in its own memory space and is accessible through the use of the password program and password read commands. ? all 64-bit password combinations are valid as a password. ? the password mode, once programmed, prevents reading the 64-bit password and further password programming. all further program and read commands to the password region are disabled and these commands are ignored. there is no means to verify what the password is after the password mode lock bit is selected. password verification is only allowed before selecting the password protection mode. ? the protection mode lock bits are not erasable. ? the exact password must be entered in order for the unlocking function to occur. if the password unlock command provided password does not match the hidden internal password, the unlock operation fails in the same manner as a programming operation on a protected sector. the p_err bit is set to one and the wip bit remains set. in this case it is a failure to change the state of the ppb lock bit because it is still protected by the lack of a valid password. ? the password unlock command cannot be accepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a password. the read status register 1 command may be used to read the wip bit to determine when the device has completed the password unlock command or is ready to accept a new password command. when a valid password is provided the password unlock command does not insert the 100 s delay before returning the wip bit to zero. ? if the password is lost after se lecting the password mode, there is no way to set the ppb lock bit.
january 8, 2014 S25FL512S_00_07 S25FL512S 71 data sheet 10. commands all communication between the host system and the s25f l512s memory device is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. commands may also have an address, instruct ion modifier, latency period, data transfer to the memory, or data transfer from the memory. all instru ction, address, and data information is transferred serially between the host system and memory device. all instructions are transferred from host to memory as a single bit serial sequence on the si signal. single bit wide commands may provide an address or data sent only on the si signal. data may be sent back to the host serially on so signal. dual or quad output commands provide an address sent to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input/output (i/o) commands provide an ad dress sent from the host as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. commands are structured as follows: ? each command begins with an eight bit (byte) instruction. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. the address may be either a 24-bit or 32-b it byte boundary address. ? the serial peripheral interface with multiple io pr ovides the option for each transfer of address and data information to be done one, two, or four bits in parallel. this enables a trade off between the number of signal connections (io bus width) and the speed of information transfer. if the host system can support a two or four bit wide io bus the memory performance can be increased by usi ng the instructions that provide parallel two bit (dual) or parallel four bit (quad) transfers. ? the width of all transfers following the instru ction are determined by the instruction sent. ? all single bits or parallel bit groups are tran sferred in most to least significant bit order. ? some instructions send instruction modifier (mode) bits following the address to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. the next command thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command ty pe is repeated in a sequence of commands. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? read latency may be zero to several sck cycles (also referred to as dummy cycles). ? all instruction, address, mode, and data information is transferred in byte granularity. addresses are shifted into the device with the most significant byte first. a ll data is transferred with t he lowest address byte sent first. following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. ? all attempts to read the flash memory array duri ng a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will c ontinue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. while a program, eras e, or write operation is in progress, it is recommended to check that the write-in progress (w ip) bit is 0 before issuing most commands to the device, to ensure the new command can be accepted. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful. ? although host software in some cases is used to di rectly control the spi interface signals, the hardware interfaces of the host system and the memory device generally handle the details of signal relationships and timing. for this reason, signal relationships and timing are not covered in detail within this software interface focused section of the docu ment. instead, the focus is on the l ogical sequence of bits transferred
72 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet in each command rather than the signal timing and relationships. following are some general signal relationship descriptions to keep in mind. for additional information on the bit level format and signal timing relationships of commands, see command protocol on page 22 . ? the host always controls the chip select (cs#), serial clock (sck), and serial in put (si) - si for single bit wide transfers. the memory drives serial out put (so) for single bit read transfers. the host and memory alternately drive the io0-io3 signa ls during dual and quad transfers. ? all commands begin with the host selecting the memory by driving cs# low before the first rising edge of sck. cs# is kept low thro ughout a command and when cs# is returned high the command ends. generally, cs# remains low for eight bit transfer mu ltiples to transfer byte granularity information. some commands will not be accepted if cs# is returned high not at an 8 bit boundary. 10.1 command set summary 10.1.1 extended addressing to accommodate addressing above 128 mb, there are three options: 1. new instructions are provided with 4-byte address, used to access up to 32 gb of memory. instruction name description code (hex) 4fast_read read fast (4-byte address) 0c 4read read (4-byte address) 13 4dor read dual out (4-byte address) 3c 4qor read quad out (4-byte address) 6c 4dior dual i/o read (4-byte address) bc 4qior quad i/o read (4-byte address) ec 4ddrfr read ddr fast (4-byte address) 0e 4ddrdior ddr dual i/o read (4-byte address) be 4ddrqior ddr quad i/o read (4-byte address) ee 4pp page program (4-byte address) 12 4qpp quad page program (4-byte address) 34 4se erase 256 kb (4-byte address) dc
january 8, 2014 S25FL512S_00_07 S25FL512S 73 data sheet 2. for backward compatibility to the 3-byte addre ss instructions, the standard instructions can be used in conjunction with the extadd bit in the bank address register (bar[7]). by default bar[7] is cleared to 0 (following power up and hardware reset), to enable 3-byte (24-bit) addressing. when set to 1, the legacy commands are changed to requ ire 4 bytes (32 bits) for the address field. the following instructions can be used in conjunction with extadd bit to switch from 3 bytes to 4 bytes of address field. 3. for backward compatibility to the 3-byte addressi ng, the standard instructions can be used in conjunction with the bank address register: a. the bank address register is used to switch between 128-mbit (16-mbyte) banks of memory, the standard 3-byte address selects an address within the bank selected by the bank address register. i. the host system writes the bank address re gister to access beyond the first 128 mbits of memory. ii. this applies to read, erase, and program commands. b. the bank register provides the high order (4th) byte of address, which is used to address the available memory at addresses greater than 16 mbytes. c. bank register bits are volatile. i. on power up, the default is bank 0 (the lowest address 16 mbytes). d. for read, the device will continuously tr ansfer out data until the end of the array. i. there is no bank to bank delay. ii. the bank address register is not updated. iii. the bank address register value is us ed only for the initial address of an access. instruction name description code (hex) read read (3-byte address) 03 fast_read read fast (3-byte address) 0b dor read dual out (3-byte address) 3b qor read quad out (3-byte address) 6b dior dual i/o read (3-byte address) bb qior quad i/o read (3-byte address) eb ddrfr read ddr fast (3-byte address) 0d ddrdior ddr dual i/o read (3-byte address) bd ddrqior ddr quad i/o read (3-byte address) ed pp page program (3-byte address) 02 qpp quad page program (3-byte address) 32 se erase 256 kb (3-byte address) d8 table 10.1 bank address map bank address register bits bank memory array address range (hex) bit 1 bit 0 0 0 0 00000000 00ffffff 0 1 1 01000000 01ffffff 1 0 2 02000000 02ffffff 1 1 3 03000000 03ffffff
74 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet table 10.2 S25FL512S command set (sorted by function) (sheet 1 of 2) function command name command description instruction value (hex) maximum frequency (mhz) (1) read device identification read_id (rems) read electronic manufacturer signature 90 133 rdid read id (jedec manufacturer id and jedec cfi) 9f 133 res read electronic signature ab 50 rsfdp read serial flash discoverable parameters 5a 133 register access rdsr1 read status register-1 05 133 rdsr2 read status register-2 07 133 rdcr read configuration register-1 35 133 wrr write register (status-1, configuration-1) 01 133 wrdi write disable 04 133 wren write enable 06 133 clsr clear status register-1 - erase/prog. fail reset 30 133 abrd autoboot register read 14 133 (quad=0) 104 (quad=1) abwr autoboot register write 15 133 brrd bank register read 16 133 brwr bank register write 17 133 brac bank register access (legacy command formerly used for deep power down) b9 133 dlprd data learning pattern read 41 133 pnvdlr program nv data learning register 43 133 wvdlr write volatile data learning register 4a 133 read flash array read read (3- or 4-byte address) 03 50 4read read (4-byte address) 13 50 fast_read fast read (3- or 4-byte address) 0b 133 4fast_read fast read (4-byte address) 0c 133 ddrfr ddr fast read (3- or 4-byte address) 0d 66 4ddrfr ddr fast read (4-byte address) 0e 66 dor read dual out (3- or 4-byte address) 3b 104 4dor read dual out (4-byte address) 3c 104 qor read quad out (3- or 4-byte address) 6b 104 4qor read quad out (4-byte address) 6c 104 dior dual i/o read (3- or 4-byte address) bb 104 4dior dual i/o read (4-byte address) bc 104 ddrdior ddr dual i/o read (3- or 4-byte address) bd 66 4ddrdior ddr dual i/o read (4-byte address) be 66 qior quad i/o read (3- or 4-byte address) eb 104 4qior quad i/o read (4-byte address) ec 104 ddrqior ddr quad i/o read (3- or 4-byte address) ed 66 4ddrqior ddr quad i/o read (4-byte address) ee 66 program flash array pp page program (3- or 4-byte address) 02 133 4pp page program (4-byte address) 12 133 qpp quad page program (3- or 4-byte address) 32 80 qpp quad page program - alternate instruction (3- or 4-byte address) 38 80 4qpp quad page program (4-byte address) 34 80 pgsp program suspend 85 133 pgrs program resume 8a 133
january 8, 2014 S25FL512S_00_07 S25FL512S 75 data sheet note: 1. for automotive in-cabin temperature range (-40c to +105c), al l maximum frequency values are 5% slower than the max values s hown. 10.1.2 read device identification there are multiple commands to read information ab out the device manufacturer, device type, and device features. spi memories from diffe rent vendors have used different commands and formats for reading information about the memories. the S25FL512S device supports the three most common device information commands. 10.1.3 register read or write there are multiple registers for reporting embedded op eration status or contro lling device configuration options. there are commands for reading or writing these registers. regi sters contain both volatile and non- volatile bits. non-volatile bits in registers are automatically erased and programmed as a single (write) operation. 10.1.3.1 monitoring operation status the host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the write in progress (wip) bit in the status register. the read from status register-1 command provides the st ate of the wip bit. the program e rror (p_err) and erase error (e_err) bits in the status register indicate whether the mo st recent program or erase command has not completed successfully. when p_err or e_err bits are set to one, the wip bit will remain set to one indicating the device remains busy. under this condition, only the clsr, wrdi, rdsr1, rdsr2, and software reset erase flash array be bulk erase 60 133 be bulk erase (alternate command) c7 133 se erase 256 kb (3- or 4-byte address) d8 133 4se erase 256 kb (4-byte address) dc 133 ersp erase suspend 75 133 errs erase resume 7a 133 one time program array otpp otp program 42 133 otpr otp read 4b 133 advanced sector protection dybrd dyb read e0 133 dybwr dyb wr ite e1 133 ppbrd ppb read e2 133 ppbp ppb program e3 133 ppbe ppb erase e4 133 asprd asp read 2b 133 aspp asp program 2f 133 plbrd ppb lock bit read a7 133 plbwr ppb lock bit write a6 133 passrd password read e7 133 passp password program e8 133 passu password unlock e9 133 reset reset software reset f0 133 mbr mode bit reset ff 133 reserved for future use mpm reserved for multi-i/o-high perf mode (mpm) a3 133 rfu reserved-18 reserved 18 rfu reserved-e5 reserved e5 rfu reserved-e6 reserved e6 table 10.2 S25FL512S command set (sorted by function) (sheet 2 of 2) function command name command description instruction value (hex) maximum frequency (mhz) (1)
76 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet commands are valid commands. a clear status regist er (clsr) followed by a write disable (wrdi) command must be sent to return the device to standby state. clsr clears the wip, p_err, and e_err bits. wrdi clears the wel bit. alternativel y, hardware reset, or software reset (reset) ma y be used to return the device to standby state. 10.1.3.2 configuration there are commands to read, write, an d protect registers that control inte rface path width, interface timing, interface address length, and so me aspects of data protection. 10.1.4 read flash array data may be read from the memory starting at any byte boundary. data bytes are sequentially read from incrementally higher byte addresses until the host ends th e data transfer by driving cs # input high. if the byte address reaches the maximum address of the memory a rray, the read will continue at address zero of the array. there are several different read comm ands to specify different access la tency and data path widths. double data rate (ddr) commands also define the addre ss and data bit relationship to both sck edges: ? the read command provides a single address bit per sck rising edge on the si signal with read data returning a single bit per sck falling edge on the so signal. this command has zero latency between the address and the returning data but is limited to a maximum sck rate of 50 mhz. ? other read commands have a latency period between the address and returning data but can operate at higher sck frequencies. the latency depends on the configuration register latency code. ? the fast read command provides a single address bit per sck rising edge on the si signal with read data returning a single bit per sck falling edge on the so signal and may operate up to 133 mhz. ? dual or quad output read commands provide address a single bit per sck rising edge on the si / io0 signal with read data returning two bits, or four bi ts of data per sck falling edge on the io0-io3 signals. ? dual or quad i/o read commands provide address two bi ts or four bits per sck rising edge with read data returning two bits, or four bits of data per sck falling edge on the io0-io3 signals. ? fast (single), dual, or quad double data rate read commands provide address one bit, two bits or four bits per every sck edge with read data returning one bit, two bits, or four bits of data per every sck edge on the io0-io3 signals. double data rate (ddr) operation is only supported for core and i/o voltages of 3 to 3.6v. 10.1.5 program flash array programming data requires two commands: write e nable (wren), and page program (pp or qpp). the page program command accepts from 1 byte up to 51 2 consecutive bytes of data (page) to be programmed in one operation. programming means that bits can eit her be left at 1, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 10.1.6 erase flash array the sector erase (se) and bulk erase (be) commands set all the bits in a sector or the entire memory array to 1. a bit needs to be first erased to 1 before programming can change it to a 0. while bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 mu st be done on a sector-wide (se) or array-wide (be) level. 10.1.7 otp, block protection, and advanced sector protection there are commands to read and program a separate one time programmable (otp) array for permanent data such as a serial number. there are commands to control a contiguous group (block) of flash memory array sectors that are protected from program and er ase operations. there are commands to control which individual flash memory array sectors are protected from progra m and erase operations.
january 8, 2014 S25FL512S_00_07 S25FL512S 77 data sheet 10.1.8 reset there is a command to reset to the default conditions present after power on to the device. there is a command to reset (exit from) the enhanced performance read modes. 10.1.9 reserved some instructions are reserved for fu ture use. in this generation of the S25FL512S some of these command instructions may be unused and not affect device operation, some may have undefined results. some commands are reserved to ensure that a legacy or alternate source device command is allowed without affect. this allows legacy software to issue some commands that are not relevant for the current generation S25FL512S device with th e assurance these commands do not cause some unexpected action. some commands are reserved for use in special versions of the fl-s not addressed by this document or for a future generation. this allows new host memory cont roller designs to plan the flexibility to issue these command instructions. the command format is defined if known at the time this document revision is published. 10.2 identification commands 10.2.1 read identific ation - rems (read_i d or rems 90h) the read_id command identifies the device manufac turer id and the device id. the command is also referred to as read electronic manufacturer and device signature (rems). read-id (rems) is only supported for backward compatibility and should not be used for new software designs. new software designs should instead make use of the rdid command. the command is initiated by shifting on si the instruct ion code ?90h? followed by a 24-bit address of 00000h. following this, the manufacturer id and the device id ar e shifted out on so starting at the falling edge of sck after address. the manufacturer id and the device id are always shifted out with the msb first. if the 24-bit address is set to 000001h, then the device id is read out first followed by the manufacturer id. the manufacturer id and device id output data toggles between address 000000h and 000001h until terminated by a low to high transition on cs# input. the maximum clock frequency for the read_id command is 133 mhz. figure 10.1 read_id (90h) command sequence table 10.3 read_id values device manufacturer id (hex) device id (hex) S25FL512S 01 19 cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction (90h) manufacturer id device id address
78 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 10.2.2 read identific ation (rdid 9fh): the read identification (rdid) comm and provides read access to manufacturer identification, device identification, and common flash interface (cfi) info rmation. the manufacturer identification is assigned by jedec. the cfi structure is defined by jedec standard. the device identification and cfi values are assigned by spansion. the jedec common flash interface (cfi) specification def ines a device information structure, which allows a vendor-specified software flash managem ent program (driver) to be used for entire families of flash devices. software support can then be device-independent, jedec manufacturer id independent, forward and backward-compatible for the specifie d flash device families. system ve ndors can standardize their flash drivers for long-term software compatibility by using the cfi values to configure a fa mily driver from the cfi information of the device in use. any rdid command issued while a program, erase, or writ e cycle is in progress is ignored and has no effect on execution of the program, erase, or write cycle that is in progress. the rdid instruction is shifte d on si. after the last bit of the rdid instru ction is shifted into the device, a byte of manufacturer identification, two bytes of device identification, extended devic e identification, and cfi information will be shifted sequentially out on so. as a whole this information is referred to as id-cfi. see id- cfi address space on page 54 for the detail description of the id-cfi contents. continued shifting of output beyond the end of the defin ed id-cfi address space will provide undefined data. the rdid command sequence is termina ted by driving cs# to the logic high state anytime during data output. the maximum clock frequency for the rdid command is 133 mhz. figure 10.2 read identification (rdid 9fh) command sequence 10.2.3 read electronic si gnature (res) (abh): the res command is used to read a single byte elec tronic signature from so. res is only supported for backward compatibility and should not be used for new software designs. new software designs should instead make use of the rdid command. the res instruction is shifted in followed by three dummy bytes onto si. after the last bit of the three dummy bytes are shifted into the device, a byte of electronic sig nature will be shifted out of so. each bit is shifted out by the falling edge of sck. the maximum clock frequency for the res command is 50 mhz. the electronic signature can be read repeatedly by applying multiples of eight clock cycles. the res command sequence is terminated by driving cs# to the logic high state anytime during data output. cs# sck si so phase 76543210 7654321076543210 instruction data 1 data n
january 8, 2014 S25FL512S_00_07 S25FL512S 79 data sheet figure 10.3 read electronic signature (res abh) command sequence 10.2.4 read serial fl ash discoverable parameters (rsfdp 5ah) the command is initiated by shifting on si the instructi on code ?5ah?, followed by a 24-bit address of 000000h, followed by eight dummy cycles. the sfdp bytes are then shifted out on so starting at the falling edge of sck after the eight dummy cycles. the sfdp bytes are always shifted out with the msb first. if the 24-bit address is set to any other value, the selected location in the sfdp space is the starting point of the data read. this enables random access to any parameter in the sfdp space. the maximum clock frequency for the rsfdp command is 133 mhz. figure 10.4 rsfdp command sequence 10.3 register access commands 10.3.1 read status regi ster-1 (rdsr1 05h): the read status register-1 (rdsr1) command allows t he status register-1 conten ts to be read from so. the status register-1 contents may be read at any time, even while a program, erase, or write operation is in progress. it is possible to read the status register-1 c ontinuously by providing multiples of eight clock cycles. the status is updated for each eight cycle read . the maximum clock frequ ency for the rdsr1 (05h) command is 133 mhz. table 10.4 res values device device id (hex) S25FL512S 19 cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction (abh) dummy device id cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
80 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.5 read status register-1 (rdsr1 05h) command sequence 10.3.2 read status regi ster-2 (rdsr2 07h): the read status register (rdsr2) co mmand allows the status register-2 contents to be read from so. the status register-2 contents may be read at any time, even while a program, erase, or write operation is in progress. it is possible to read the status register-2 c ontinuously by providing multiples of eight clock cycles. the status is updated fo r each eight cycle read. th e maximum clock frequency fo r the rdsr2 command is 133 mhz. figure 10.6 read status register-2 (rdsr2 07h) command sequence 10.3.3 read configurati on register (rdcr 35h): the read configuration register (rdcr) command allo ws the configuration regi ster contents to be read from so. it is possible to read the configuration regist er continuously by providing multiples of eight clock cycles. the configuration register contents may be read at any time , even while a progra m, erase, or write operation is in progress. figure 10.7 read configuration register (rdcr 35h) command sequence 10.3.4 bank register read (brrd 16h) the read the bank register (brrd) command allows t he bank address register contents to be read from so. the instruction is first shifted in from si. then the 8-bit bank register is shifted out on so. it is possible to read the bank regi ster continuously by provid ing multiples of eight clo ck cycles. the maximum operating clock frequency for the brrd command is 133 mhz. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status cs# sck si so phase 76543210 7654321076543210 instruction register read repeat register read
january 8, 2014 S25FL512S_00_07 S25FL512S 81 data sheet figure 10.8 read bank register (brrd 16h) command 10.3.5 bank register write (brwr 17h) the bank register write (brwr) command is used to write address bits above a23, into the bank address register (bar). the command is also used to write the extended address control bit (extadd) that is also in bar[7]. bar provides the high order addresses needed by devices having more than 128 mbits (16 mbytes), when using 3-byte address commands without extended addressing enabled (bar[7] extadd = 0). because this command is part of the addressing method and is not changing data in the flash memory, this command does not require the wren command to precede it. the brwr instruction is entered, followed by the data byte on si. the bank register is one data byte in length. the brwr command has no effect on the p_err, e_er r or wip bits of the status and configuration registers. any bank address bit reserved for the future should always be written as a 0. figure 10.9 bank register write (brwr 17h) command 10.3.6 bank register access (brac b9h): the bank register read and write commands provide full access to the bank address register (bar) but they are both commands that are not present in legacy spi memory devices. host system spi memory controller interfaces may not be able to easily s upport such new commands. the bank register access (brac) command uses the same command code and format as the deep power down (dpd) command that is available in legacy spi memories. the fl-s family does not support a dpd feature but assigns this legacy command code to the brac command to enable write access to the bank address register for legacy systems that are able to send the legacy dpd (b9h) command. when the brac command is sent, the fl-s family device will then interpret an immediately following write register (wrr) command as a write to the lower address bits of the bar. a wren command is not used between the brac and wrr commands. only the lower two bits of the first data byte following the wrr command code are used to load bar[1:0]. the upper bits of that byte and the content of the optional wrr command second data byte are ignored. following the wrr command the access to bar is closed and the device interface returns to the standby state. the co mbined brac followed by wrr command sequence has no affect on the value of the extadd bit (bar[7]). commands other than wrr may immediately follow brac and execute normally. however, any command other than wrr, or any other s equence in which cs# goes low and returns high, following a brac command, will close the access to bar and return to the normal interpretation of a wrr command as a write to status register-1 and the configuration register. the brac + wrr sequence is allowed only when the device is in standby, program suspend, or erase suspend states. this command sequence is illegal w hen the device is performing an embedded algorithm or when the program (p_err) or erase (e _err) status bits are set to 1. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck si so phase 7654321076543210 instruction input data
82 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.10 brac (b9h) command sequence 10.3.7 write regi sters (wrr 01h): the write registers (wrr) command allows new values to be written to both the status register-1 and configuration register. before the write registers (w rr) command can be accepted by the device, a write enable (wren) command must be received. after t he write enable (wren) command has been decoded successfully, the device will set the write enable latch (wel) in the status regi ster to enable any write operations. the write registers (wrr) command is entered by shifting the instruction and the data bytes on si. the status register is one data byte in length. the write registers (wrr) command will set the p_err or e_err bits if there is a failure in the wrr operation. any status or configurat ion register bit reserved for t he future must be written as a 0. cs# must be driven to the logic high st ate after the eighth or sixteenth bit of data has been latc hed. if not, the write registers (wrr) command is not executed. if cs# is driven high after the eighth cycle then only the status register-1 is written; otherwise, after the sixt eenth cycle both the status and configuration registers are written. when the configuration register quad bit cr[1] is 1, only the wrr command format with 16 data bits may be used. as soon as cs# is driven to the logic high state, the self-timed write registers (wrr) operation is initiated. while the write registers (wrr) operation is in progre ss, the status register ma y still be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a 1 during the self-timed write registers (wrr) operation, and is a 0 when it is co mpleted. when the write registers (wrr) operation is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the wrr command is 133 mhz. figure 10.11 write registers (wrr 01h) co mmand sequence ? 8 data bits figure 10.12 write registers (wrr 01h) command sequence ? 16 data bits cs# sck si so phase 76543210 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register-1 cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register-1 input configuration register
january 8, 2014 S25FL512S_00_07 S25FL512S 83 data sheet the write registers (wrr) command allows the user to change the values of the block protect (bp2, bp1, and bp0) bits to define the size of the area that is to be treated as read-only . the write registers (wrr) command also allows the user to set the status register write disable (srw d) bit to a 1 or a 0. the status register write disable (srwd) bit and write protec t (wp#) signal allow the bp bits to be hardware protected. when the status register write disable (s rwd) bit of the status register is a 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (w el) bit has previously been set by a write enable (wren) command, regardless of the whether write protect (wp#) signal is driven to the logic high or logic low state. when the status register writ e disable (srwd) bit of the status register is set to a 1, two cases need to be considered, depending on the st ate of write protect (wp#): ? if write protect (wp#) signal is driven to the logic high state, it is possible to write to the status and configuration registers provided that the write enable latch (wel) bit has previously been set to a ?1? by initiating a write enable (wren) command. ? if write protect (wp#) signal is driven to the logic low state, it is not possible to write to the status and configuration registers even if the write enable latch (wel) bit has previously been set to a 1 by a write enable (wren) command. attempts to write to the st atus and configuration r egisters are rejected, and are not accepted for execution. as a consequence, all th e data bytes in the memory area that are protected by the block protect (bp2, bp1, bp0) bits of the stat us register, are also hardware protected by wp#. the wp# hardware protection can be provided: ? by setting the status register write disable (srwd) bi t after driving write protect (wp#) signal to the logic low state; ? or by driving write protect (wp#) signal to the logic lo w state after setting the status register write disable (srwd) bit to a 1. the only way to release the hardware protection is to pull the write protect (wp#) signal to the logic high state. if wp# is permanently tied high, hardware protection of the bp bits can never be activated. notes: 1. the status register originally shows 00h when the device is first shipped from spansion to the customer. 2. hardware protection is disabled when quad mode is enabled (qua d bit = 1 in configuration register). wp# becomes io2; therefor e, it cannot be utilized. the wrr command has an alternate function of lo ading the bank address register if the command immediately follows a brac command. see bank register access (brac b9h): on page 81 . table 10.5 block protection modes wp# srwd bit mode write protection of registers memory content protected area unprotected area 11 software protected status and configuration registers are writable (if wren command has set the wel bit). the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register can be changed protected against page program, quad input program, sector erase, and bulk erase ready to accept page program, quad input program and sector erase commands 10 00 01 hardware protected status and configuration registers are hardware write protected. the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register cannot be changed protected against page program, sector erase, and bulk erase ready to accept page program or erase commands
84 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 10.3.8 write en able (wren 06h) the write enable (wren) command sets the write enable latch (wel) bit of the status register 1 (sr1[1]) to a 1. the write enable latch (wel) bit must be set to a 1 by issuing the write enable (wren) command to enable write, program and erase commands. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. without cs# being driven to the logic high state afte r the eighth bit of the instruction byte has been latched in on si, the write enable op eration will not be executed. figure 10.13 write enable (wren 06h) command sequence 10.3.9 write disab le (wrdi 04h): the write disable (wrdi) command sets the write enable latch (wel) bit of the status register-1 (sr1[1]) to a 0. the write enable latch (wel) bit may be set to a 0 by issuing the write disable (wrdi) command to disable page program (pp), sector erase (se), bulk erase (be), write registers (wrr) , otp program (otpp), and other commands, that require wel be set to 1 for exec ution. the wrdi command can be used by the user to protect memory areas against inadvertent writes that can possibly corrupt the contents of the memory. the wrdi command is ignored during an embedded operation while wip bit =1. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. without cs# being driven to the logic high state afte r the eighth bit of the instruction byte has been latched in on si, the write disable operation will not be executed. figure 10.14 write disable (wrdi 04h) command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 76543210 instruction
january 8, 2014 S25FL512S_00_07 S25FL512S 85 data sheet 10.3.10 clear status r egister (clsr 30h): the clear status register command resets bit sr1[5] (erase fail flag) and bit sr1[6] (program fail flag). it is not necessary to set the wel bit before the clear sr command is executed. the clear sr command will be accepted even when the device re mains busy with wip set to 1, as the device does re main busy when either error bit is set. the wel bit will be unchanged after this command is executed. figure 10.15 clear status register (clsr 30h) command sequence 10.3.11 autoboot spi devices normally require 32 or more cycles of command and address shifting to initiate a read command. and, in order to read boot code from an spi device, the host memory contro ller or processor must supply the read command from a hardwired state machine or from some host processor internal rom code. parallel nor devices need only an initial address, supplied in parallel in a single cycle, and initial access time to start reading boot code. the autoboot feature allows the host memory contro ller to take boot code from an S25FL512S device immediately after the end of reset, without having to send a read command. this saves 32 or more cycles and simplifies the logic needed to initiate the reading of boot code. ? as part of the power up reset, hardware reset, or command reset process the autoboot feature automatically starts a read access from a pre-specified address. at the time the reset process is completed, the device is ready to deliver code from the starting address. the host memory controller only needs to drive cs# signal from high to low and begin toggling the sck signal. the S25FL512S device will delay code output for a pre- specified number of clock cycles before code streams out. ? the auto boot start delay (absd) fi eld of the autoboot register spec ifies the initial delay if any is needed by the host. ? the host cannot send commands during this time. ? if absd = 0, the maximum sck frequency is 50 mhz. ? if absd > 0, the maximum sck frequency is 133 mhz if the quad bit cr1[1] is 0 or 104 mhz if the quad bit is set to 1. ? the starting address of the boot code is selected by the value programmed into the autoboot start address (absa) field of the autoboot register which specifies a 512 byte boundary aligned location; the default address is 00000000h. ? data will continuously shif t out until cs# returns high. ? at any point after the first data byte is transferred, when cs# returns high, the spi device will reset to standard spi mode; able to accept normal command operations. ? a minimum of one byte must be transferred. ? autoboot mode will not initiate again unti l another power cycle or a reset occurs. ? an autoboot enable bit (abe) is set to enable the autoboot feature. the autoboot register bits are non-volatile and provide: ? the starting address (512-byte boundary), set by th e autoboot start address (absa). the size of the absa field is 23 bits fo r devices up to 32-gbit. ? the number of initial delay cycl es, set by the autoboot start delay (absd) 8-bit count value. ? the autoboot enable. cs# sck si so phase 76543210 instruction
86 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet if the configuration register quad bi t cr1[1] is set to 1, the boot code will be provided 4 bits per cycle in the same manner as a read quad out command. if the quad bit is 0 the code is delivered serially in the same manner as a read command. figure 10.16 autoboot sequence (cr1[1]=0) figure 10.17 autoboot sequence (cr1[1]=1) 10.3.12 autoboot regi ster read (abrd 14h) the autoboot register read command is shifted into si. then the 32-bit autoboot register is shifted out on so, least significant byte first, most significant bit of each byte first. it is po ssible to read the autoboot register continuously by providing multiples of 32 clo ck cycles. if the quad bit cr1[1] is cleared to 0, the maximum operating clock frequency for abrd command is 1 33 mhz. if the quad bit cr1[1] is set to 1, the maximum operating clock frequency for abrd command is 104 mhz. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 wait states (absd) data 1 data n cs# sck io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 wait states (absd) data 1 data 2 data 3 data 4 data 5 ...
january 8, 2014 S25FL512S_00_07 S25FL512S 87 data sheet figure 10.18 autoboot register read (abrd 14h) command 10.3.13 autoboot regist er write (abwr 15h) before the abwr command can be accepted, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the st atus register to enable any write operations. the abwr command is entered by shifting the instruction a nd the data bytes on si, leas t significant byte first, most significant bit of each byte firs t. the abwr data is 32 bits in length. the abwr command has status reported in status register-1 as both an erase and a programming operation. an e_err or a p_err may be set depending on whether the erase or programming phase of updating the register fails. cs# must be driven to the logic high state after the 32nd bit of data has been latched. if not, the abwr command is not executed. as soon as cs# is driven to t he logic high state, the self-timed abwr operation is initiated. while the abwr operation is in progress, stat us register-1 may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed abwr operation, and is a 0. when it is completed. when the abwr cycle is co mpleted, the write enable la tch (wel) is set to a 0. the maximum clock frequency for the abwr command is 133 mhz. figure 10.19 autoboot register write (abwr) command 10.3.14 program nvdlr (pnvdlr 43h) before the program nvdlr (pnvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device will set the write enab le latch (wel) to enable the pnvdlr operation. the pnvdlr command is entered by shifting the instruction and the data byte on si. cs# must be driven to the logic high state after the eighth (8th) bit of data has been latched. if not, the pnvdlr command is not executed. as soon as cs# is driv en to the logic high stat e, the self-timed pnvdlr operation is initiated. while the pnvdlr operation is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the writ e-in progress (wip) bit is a 1 during the self-timed pnvdlr cycle, and is a 0. when it is completed. the pnvdlr operation can report a program error in the p_err bit of the status register. when the pnvdlr operation is completed, the write enable latch (wel) is set to a 0 the maximum clock frequency for the pnvdlr command is 133 mhz. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 instruction input data 1
88 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.20 program nvdlr (pnvdlr 43h) command sequence 10.3.15 write vdlr (wvdlr 4ah) before the write vdlr (wvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device will set the write enable latch (wel) to enable wvdlr operation. the wvdlr command is entered by shifting th e instruction and the data byte on si. cs# must be driven to the logic high state after the eighth (8th) bit of data has been latched. if not, the wvdlr command is not executed. as soon as cs# is driven to the logi c high state, the wvdlr operation is initiated with no delays. the maximum clock frequency for the pnvdlr command is 133 mhz. figure 10.21 write vdlr (wvdlr 4ah) command sequence 10.3.16 data learning pa ttern read (dlprd 41h) the instruction is shifted on si, then the 8-bit dlp is shifted out on so. it is possible to read the dlp continuously by providing multiples of eight clock cycles. the maximum operating clock frequency for the dlprd command is 133 mhz. figure 10.22 dlp read (dlprd 41h) command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n
january 8, 2014 S25FL512S_00_07 S25FL512S 89 data sheet 10.4 read memory array commands read commands for the main flash array provide many options for prior generat ion spi compatibility or enhanced performance spi: ? some commands transfer address or data on each risi ng edge of sck. these are called single data rate commands (sdr). ? some sdr commands transfer address one bit per rising edge of sck and return data 1, 2, or 4 bits of data per rising edge of sck. these are called read or fast read for 1-bit data; dual output read for 2-bit data, and quad output for 4-bit data. ? some sdr commands transfer both address and data 2 or 4 bits per rising edge of sck. these are called dual i/o for 2 bit and quad i/o for 4 bit. ? some commands transfer address and data on both th e rising edge and falling edge of sck. these are called double data rate (ddr) commands. ? there are ddr commands for 1, 2, or 4 bits of addr ess or data per sck edge. these are called fast ddr for 1-bit, dual i/o ddr for 2-bit, and quad i/o ddr for 4-bit per edge transfer. all of these commands begin with an in struction code that is transferred one bit per sck rising edge. the instruction is followed by either a 3- or 4-byte address transferred at sdr or ddr. commands transferring address or data 2 or 4 bits per clock edge are called multiple i/o (mio) commands. for fl-s devices at 256 mbits or higher density, the traditi onal spi 3-byte addresses are unable to directly address all locations in the memory array. these device have a bank address r egister that is used with 3-byte address commands to supply the high order address bits beyond the addre ss from the host system. the default bank address is zero. commands are provided to load and read the bank address register. these devices may also be configured to take a 4-byte address from the host system wit h the traditiona l 3-byte address commands. the 4-byte address mode for traditional commands is activat ed by setting the external address (extadd) bit in the bank address register to 1. the quad i/o commands provide a performance improvem ent option controlled by mode bits that are sent following the address bits. the mode bits indicate whet her the command following the end of the current read will be another read of the same type, without an instru ction at the beginning of the read. these mode bits give the opti on to eliminate the instruct ion cycles when doing a series of quad i/o read accesses. a device ordering option provides an enhanced high performance option by adding a similar mode bit scheme to the ddr fast read, dual i/o, and dual i/o ddr commands, in addition to the quad i/o command. some commands require delay cycles foll owing the address or mode bits to allow time to access the memory array. the delay cycles are traditio nally called dummy cycles. the dummy cycles are ignored by the memory thus any data provided by th e host during these cycles is ?don?t care ? and the host may also leave the si signal at high impedance during the dummy cycles. when mio commands are us ed the host must stop driving the io signals (outputs are high impedance) before the end of last dummy cycle. when ddr commands are used the host must not drive the i/o signals during any dummy cycle. the number of dummy cycles varies with the sck frequency or performance option selected via the configuration r egister 1 (cr1) latency code (lc). dummy cycles are measured from sck falling edge to next sck falling edge. spi outputs are traditionally driven to a new value on the falli ng edge of each sck. zero dummy cycles means the returning data is driven by the memory on the same fa lling edge of sck that the host stops driving address or mode bits. the ddr commands may optionally have an 8-edge data learning pattern (dlp) driven by the memory, on all data outputs, in the dummy cyc les immediately before the start of data. the dlp can help the host memory controller determine the phase shift from sck to data edges so that the memory controller can capture data at the c enter of the data eye. when using sdr i/o commands at higher sck frequenc ies (>50 mhz), an lc that provides 1 or more dummy cycles should be selected to allow additional time for the host to stop drivin g before the memory starts driving data, to minimize i/o driver conflict. when u sing ddr i/o commands with the dlp enabled, an lc that provides 5 or more dummy cycles should be sele cted to allow 1 cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle dlp. each read command ends when cs# is returned high at any point during data return. cs# must not be returned high during the mode or dummy cycles before data returns as this may cause mode bits to be captured incorrectly; making it inde terminate as to whether the device remains in enhanced high performance read mode.
90 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 10.4.1 read (read 03h or 4read 13h): the instruction ? 03h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 03h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 13h is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, are shifted out on so. the maximum operating clock frequency for the read command is 50 mhz. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. figure 10.23 read command sequence (read 03h or 13h) 10.4.2 fast read (fast_read 0bh or 4fast_read 0ch): the instruction ? 0bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 0bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 0ch is followed by a 4-byte address (a31-a0) the address is followed by zero or eight dummy cy cles depending on the latency code set in the configuration register. the dummy cycles allow the device internal circuits additional time for accessing the initial address location. during th e dummy cycles the data value on so is ?don?t care? and may be high impedance. then the memory contents, at th e address given, are shifted out on so. the maximum operating clock frequency for fast read command is 133 mhz. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. figure 10.24 fast read (fast_read 0bh or 0ch) command sequence with read latency cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data n cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
january 8, 2014 S25FL512S_00_07 S25FL512S 91 data sheet figure 10.25 fast read command (fast_read 0bh or 0ch) sequence without read latency 10.4.3 dual output read (d or 3bh or 4dor 3ch): the instruction ? 3bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 3bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 3ch is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, is shi fted out two bits at a time through io0 (si) and io1 (so). two bits are shifted out at the sck fr equency by the falling edge of the sck signal. the maximum operating clock frequency for the dual ou tput read command is 104 mhz. for dual output read commands, there are zero or ei ght dummy cycles required after the la st address bit is shifted into si before data begins shifting out of io0 and io1. this la tency period (i.e., dummy cycles) allows the device?s internal circuitry enough time to read from the initia l address. during the dummy cycles, the data value on si is a ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck (refer to table 8.7, latency codes for sdr enhanced high performance on page 60 ). the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. figure 10.26 dual output read command sequence (3 -byte address, 3bh [extadd=0], lc=10b) cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data n cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 23 22 21 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction 8 dummy cycles data 1 data 2 address
92 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.27 dual output read command sequence (4-byte address, 3ch or 3bh [extadd=1, lc=10b]) figure 10.28 dual output read command sequence (4-byte address, 3ch or 3bh [extadd=1, lc=11b]) 10.4.4 quad output read (q or 6bh or 4qor 6ch): the instruction ? 6bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 6bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 6ch is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, is shi fted out four bits at a time through io0-io3. each nibble (4 bits) is shifted out at the sck frequency by the falling edge of the sck signal. the maximum operating clock frequency for quad output read command is 104 mhz. for quad output read mode, there may be dummy cycles required after t he last address bit is shifted into si before data begins shifting out of io0-io3. this la tency period (i.e., dummy cycles) allows the device?s internal circuitry enough time to set up for the initial address. during t he dummy cycles, the data value on io0-io3 is a ?don?t care? and may be high imped ance. the number of dummy cycles is determined by the frequency of sck (refer to table 8.7, latency codes for sdr enhanced high performance on page 60 ). the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. the quad bit of configuration register must be set (cr bit1=1) to enable the quad mode capability. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 31 30 29 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction 8 dummy cycles data 1 data 2 address cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 31 30 29 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction data 1 data 2 address
january 8, 2014 S25FL512S_00_07 S25FL512S 93 data sheet figure 10.29 quad output read (qor 6bh or 4qor 6ch) command sequence with read latency figure 10.30 quad output read (qor 6bh or 4qor 6ch) command sequence without read latency 10.4.5 dual i/o read (dio r bbh or 4dior bch): the instruction ? bbh (extadd=0) is followed by a 3-byte address (a23-a0) or ? bbh (extadd=1) is followed by a 4-byte address (a31-a0) or ? bch is followed by a 4-byte address (a31-a0) the dual i/o read commands improve throughput with two i/o signals ? io0 (si) and io1 (so). it is similar to the dual output read command but takes input of the address two bits per sck rising edge. in some applications, the reduced address input time might allow fo r code execution in place (xip) i.e. directly from the memory device. the maximum operating clock frequency for dual i/o read is 104 mhz. for the dual i/o read command, there is a latency requir ed after the last address bits are shifted into si and so before data begins shifting out of io0 and io1. t here are different ordering part numbers that select the latency code table used for this command, either th e high performance lc (hplc) table or the enhanced high performance lc (ehplc) table. the hplc table does not provide cycles for mode bits so each dual i/ o read command starts with the 8 bit instruction, fo llowed by address, followed by a latency period. this latency period (dummy cycles) allows the device internal circuitr y enough time to access data at the initial address. during the dummy cycles, the data value on si and so are ?don?t care? and may be high impedance. the number of du mmy cycles is determined by the frequency of sck ( table 8.7, latency codes for sdr enhanced high performance on page 60 ). the number of dummy cycles is set by the lc bits in the configuration register (cr1). the ehplc table does provide cycles for mode bits so a series of dual i/o read commands may eliminate the 8-bit instruction after the first dual i/o read comm and sends a mode bit pattern of axh that indicates the following command will also be a dual i/o read comma nd. the first dual i/o read command in a series starts with the 8-bit instruct ion, followed by address, followed by four cycles of mode bits, followed by a latency period. if the mode bit pattern is axh the next command is assumed to be an additional dual i/o read cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address dummy d1 d2 d3 d4 d5 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address data 1 data 2 data 3 data 4 data 5 ...
94 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet command that does not provide instruction bits. that command starts with address, followed by mode bits, followed by latency. the enhanced high performance feature removes the need for the instruction sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bits control the length of the next dual i/o read command through the inclusion or exclusion of the first byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t care? (?x?) and may be high impedance. if the mode bits equal axh, then the device remains in dual i/o enhanced high performance read mode and the next address can be entered (after cs# is raised high and then asserted low) without the bbh or bch instruction, as shown in figure 10.34 ; thus, eliminating eight cycles for the command seq uence. the follo wing sequences will release the device from dual i/o enhanced high performance read mode; after which, the device can accept standard spi commands: 1. during the dual i/o enhanced high performance command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from dual i/o read enhanced high performance read mode. during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0 and io1) are not set for a valid instruction sequence, then t he device will be released from dual i/o enhanced high performance read mode. note that the four mode bit cycles are part of the device?s internal circuitry latency time to access the initial address after the last addre ss cycle that is clocked into io0 (si) and io1 (so). it is important that the i/o signals be set to high-impedance at or before the falling edge of the first data out clock. at higher clock speeds the time available to tu rn off the host out puts before the memory device begins to drive (bus turn around) is diminished. it is allowed and may be helpful in preventing i/o signal contention, for the host system to turn off the i/o signal outputs (make them high impedance) during the last two ?don?t care? mode cycles or during any dummy cycles. following the latency period the memory content, at the address given, is shifted out two bits at a time through io0 (si) and io1 (so). two bits are shifted out at the sck frequency at the falling edge of sck signal. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. figure 10.31 dual i/o read command sequence (3-byt e address, bbh [extadd=0], hplc=00b) cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 22 20 18 0 6 4 2 0 6 4 2 0 23 21 19 1 7 5 3 1 7 5 3 1 instruction address 4 dummy data 1 data 2
january 8, 2014 S25FL512S_00_07 S25FL512S 95 data sheet figure 10.32 dual i/o read command sequence (4-byt e address, bbh [extadd=1], hplc=10b) figure 10.33 dual i/o read command sequence (4-byte address, bch or bbh [extadd=1], ehplc=10b) figure 10.34 continuous dual i/o read command sequence (4-byte address, bch or bbh [extadd=1], ehplc=10b) 10.4.6 quad i/o read (qio r ebh or 4qior ech): the instruction ? ebh (extadd=0) is followed by a 3-byte address (a23-a0) or ? ebh (extadd=1) is followed by a 4-byte address (a31-a0) or ? ech is followed by a 4-byte address (a31-a0) the quad i/o read command improves throughput with four i/o signals ? io0-io3. it is similar to the quad output read command but allows input of the address bi ts four bits per serial sck clock. in some applications, the reduced in struction overhead might allow for co de execution (xip) directly from the S25FL512S device. the quad bit of the configuration register must be set (cr bit1=1) to enable the quad capability of the S25FL512S device. the maximum operating clock frequency for quad i/o read is 104 mhz. for the quad i/o read command, there is a latency requir ed after the mode bits (described below) before data begins shifting out of io0-io3. this latency peri od (i.e., dummy cycles) allows the device?s internal circuitry enough time to access data at the initial address. during latency cycles, th e data value on io0-io3 are ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck and the latency code table (refer to table 8.7, latency codes for sdr enhanced high performance cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 28 26 0 6 4 2 0 6 4 2 0 31 29 27 1 7 5 3 1 7 5 3 1 instruction 6 dummy data 1 data 2 address cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2 cs# sck io0 io1 phase 6 4 2 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 data n address mode dum data 1 data 2
96 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet on page 60 ). there are different ordering part numbers that select the latency code table used for this command, either the high performance lc (hplc) ta ble or the enhanced high performance lc (ehplc) table. the number of dummy cycles is set by the lc bits in the configuration register (cr1). however, both latency code tables use the same latency values for the quad i/o read command. following the latency period, the memory contents at the address given, is shifted out four bits at a time through io0-io3. each nibble (4 bits) is shifted ou t at the sck frequency by the falling edge of the sck signal. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. address jumps can be done without the need for additional quad i/o read instructions. this is controlled through the setting of the mode bits (after the address sequence, as shown in figure 10.35 on page 96 or figure 10.37 on page 97 ). this added feature removes the need fo r the instruction sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bits control the length of the next quad i/o instruction through t he inclusion or exclusion of the first byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t care? (?x?). if the mode bits equal axh, then the device remains in quad i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the ebh or ech instruction, as shown in figure 10.36 on page 97 or figure 10.38 on page 97 ; thus, eliminating eight cycles for the command sequence. the following sequences will release the device from quad i/o high performanc e read mode; after which, the device can accept standard spi commands: 1. during the quad i/o read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from quad i/o high performance read mode. during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0-io3) are not set for a valid instruction sequence, then the device will be released from quad i/o high performance read mode. note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the device?s internal circuitry latency time to access the in itial address after the last address cycle that is clocked into io0-io3. it is important that the io0-io3 signal s be set to high-impedance at or before the falling edge of the first data out clock. at higher clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. it is allowed and may be helpful in preventing io0-io3 signal contention, for the host system to turn off the io0- io3 signal outputs (make them high impedance) during the last ?don?t care? mode cycle or during any dummy cycles. cs# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. figure 10.35 quad i/o read command sequence (3-byte address, ebh [extadd=0], lc=00b) cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 4 0 4 0 4 0 4 0 4 0 4 0 21 5 1 5 1 5 1 5 1 5 1 5 1 22 6 2 6 2 6 2 6 2 6 2 6 2 23 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4
january 8, 2014 S25FL512S_00_07 S25FL512S 97 data sheet figure 10.36 continuous quad i/o read command sequence (3-byte address), lc=00b figure 10.37 quad i/o read command sequence (4-byte address, ech or ebh [extadd=1], lc=00b) figure 10.38 continuous quad i/o read command sequence (4-byte address), lc=00b 10.4.7 ddr fast read ( ddrfr 0dh, 4ddrfr 0eh) the instruction ? 0dh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 0dh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 0eh is followed by a 4-byte address (a31-a0) the ddr fast read command improves throughput by transferring address and data on both the falling and rising edge of sck. it is similar to the fast read comm and but allows transfer of address and data on every edge of the clock. the maximum operating clock frequency for ddr fast read command is 66 mhz. for the ddr fast read command, there is a latency requir ed after the last address bi ts are shifted into si before data begins shifting out of so. there are differ ent ordering part numbers that select the latency code table used for this command, either the high pe rformance lc (hplc) table or the enhanced high cs# sck io0 io1 io2 io3 phase 4 0 4 0 20 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 21 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 22 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 23 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 d n address mode dummy d1 d 2 d 3 d 4 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 4 0 4 0 4 0 4 0 4 0 4 0 29 5 1 5 1 5 1 5 1 5 1 5 1 30 6 2 6 2 6 2 6 2 6 2 6 2 31 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d 1 d 2 d 3 d 4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 28 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 29 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 30 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 31 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 d n address mode dummy d 1 d 2 d 3 d 4
98 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet performance lc (ehplc) table. the hplc table does not provide cycles for mode bits so each ddr fast read command starts with the 8-bit instruction, followed by address, followed by a latency period. this latency period (dummy cycles) allows the device internal circuitr y enough time to access data at the initial address. during the dummy cycles, the data value on si is ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck ( table 8.7, latency codes for sdr enhanced high performance on page 60 ). the number of dummy cycles is set by the lc bits in the configuration register (cr1). then the memory contents, at the address given, is shi fted out, in ddr fashion, one bit at a time on each clock edge through so. each bit is shifted out at the sck frequency by the rising and falling edge of the sck signal. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. the ehplc table does provide cycles for mode bits so a series of ddr fast read co mmands may eliminate the 8-bit instruction after the first ddr fast read comm and sends a mode bit pattern of complementary first and second nibbles, e.g. a5h, 5ah, 0fh, etc., that indica tes the following command will also be a ddr fast read command. the first ddr fast read command in a seri es starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, follo wed by a latency period. if the mode bit pattern is complementary the next command is assumed to be an additional ddr fast read command that does not provide instruction bits. that command starts with address, followed by mode bits, followed by latency. when the ehplc table is used, address jumps can be done without the need for additional ddr fast read instructions. this is controlled through the setting of t he mode bits (after the address sequence, as shown in figure 10.39 on page 99 and figure 10.41 on page 99 . this added feature removes the need for the eight bit sdr instruction sequence to reduce initial access ti me (improves xip performance). the mode bits control the length of the next ddr fast read operation through th e inclusion or exclusion of the first byte instruction code. if the upper nibble (io[7:4]) and lower nibble (i o[3:0]) of the mode bits are complementary (i.e. 5h and ah) then the next address can be entered (after cs# is raised high and then asserted low) without requiring the 0dh or 0eh instruction, as shown in figure 10.40 and figure 10.42 , thus, eliminating eight cycles from the command sequence. the following sequences will release the device from this continuous ddr fast read mode; after which, the device c an accept standard spi commands: 1. during the ddr fast read command sequence, if the mode bits are not complementary the next time cs# is raised high the device will be re leased from the continuous ddr fast read mode. 2. during any operation, if cs# togg les high to low to high for eight cycles (or less) and data input (si) are not set for a valid instruction sequence, then the device will be released from ddr fast read mode. cs# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. the hold function is not valid during any part of a fast ddr command. although the data learning pattern (dlp) is programma ble, the following example shows example of the dlp of 34h. the dlp 34h (or 00110100) will be driven on eac h of the active outputs (i.e. all four ios on a x4 device, both ios on a x2 device and the single so out put on a x1 device). this pattern was chosen to cover both dc and ac data transition scenari os. the two dc transition scenarios include data low for a long period of time (two half clocks) followed by a high going tr ansition (001) and the comple mentary low going transition (110). the two ac transition scenarios include data low for a short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). the dc transitions will typically occur with a starting point cl oser to the supply rail than the ac transitions that may not have fully settled to their steady state (dc) levels. in many case s the dc tra nsitions will bound the beginning of the data valid period and the ac transitions will bound the ending of the data valid period. these transitions will allow the host controller to identify the beginning and ending of the valid data eye. once the data eye has been characterized the optimal data capture point can be chosen. see section 8.6.11, spi ddr data learning registers on page 64 for more details.
january 8, 2014 S25FL512S_00_07 S25FL512S 99 data sheet figure 10.39 ddr fast read initial access (3-byte address, 0dh [ext add=0, ehplc=11b]) figure 10.40 continuous ddr fast read subsequent access (3-byte address [ext add=0, ehplc=11b]) figure 10.41 ddr fast read initial access (4-byte addr ess, 0eh or 0dh [e xtadd=1], ehplc=01b) note: 1. example dlp of 34h (or 00110100). figure 10.42 continuous ddr fast read subsequent access (4-byte address [ext add=1], ehplc=01b) note: 1. example dlp of 34h (or 00110100). cs# sck si so phase 7 6 5 4 3 2 1 0 23 22 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address mode dummy data 1 data 2 cs# sck io0 io1 phase 23 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 address mode dum data 1 d2 cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 instruction address mode dlp data 1 d2 cs# sck si so phase 31 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 address mode dlp data 1 d2
100 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.43 ddr fast read subsequent access (4-byte address, hplc=01b) 10.4.8 ddr dual i/ o read (bdh, beh) the instruction ? bdh (extadd=0) is followed by a 3-byte address (a23-a0) or ? bdh (extadd=1) is followed by a 4-byte address (a31-a0) or ? beh is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, is shift ed out, in a ddr fashion, two bits at a time on each clock edge through io0 (si) and io1 (so). two bits are shifted out at the sck frequency by the rising and falling edge of the sck signal. the ddr dual i/o read command improves throughput wit h two i/o signals ? io0 (si) and io1 (so). it is similar to the dual i/o read command but transfers tw o address, mode, or data bits on every edge of the clock. in some applications, the redu ced instruction overhead might allo w for code execution (xip) directly from the S25FL512S device. the maximum operating clock frequency for ddr dual i/o read command is 66 mhz. for ddr dual i/o read commands, there is a latency requi red after the last address bits are shifted into io0 and io1, before data begins shifting out of io0 and io 1. there are different orderi ng part numbers that select the latency code table used for this command, either t he high performance lc (hplc) table or the enhanced high performance lc (ehplc) table. the number of latency (dummy) clocks is determined by the frequency of sck (refer to table 8.6, latency codes for ddr high performance on page 59 or table 8.8, latency codes for ddr enhanced high performance on page 60 ). the number of dummy cycles is set by the lc bits in the configuration register (cr1). the hplc table does not provide cycles for mode bits so each dual i/o command starts with the 8 bit instruction, followed by address, followed by a latency period. this latency period allows the device?s internal circuitry enough time to access the initial address. du ring these latency cycles, the data value on si (io0) and so (io1) are ?don?t care? and may be high impedance. when the data learning pattern (dlp) is enabled the host system must not drive the io signals during the dummy cycles. the io signals must be left high impedance by the host so that the memory devi ce can drive the dlp during the dummy cycles. the ehplc table does provide cycles for mode bits so a series of dual i/o ddr commands may eliminate the 8 bit instruction after the first command sends a complementary mode bit pattern, as shown in figure 10.44 and figure 10.46 on page 102 . this added feature removes the need for the eight bit sdr instruction sequence and dramatically reduces initial access times (improves xip performance). the mode bits control the length of the next ddr dual i/o read operation through the inclusion or exclusion of the first byte instruction code. if the upper nibble (io[7:4] ) and lower nibble (io[3: 0]) of the mode bits are complementary (i.e. 5h and ah) the device transitions to continuous ddr dual i/o read mode and the next address can be entered (after cs# is raised high and t hen asserted low) without requiring the bdh or beh instruction, as shown in figure 10.45 on page 101 , and thus, eliminating ei ght cycles from the command sequence. the following sequences will release the device from continuous ddr dual i/o read mode; after which, the device can accept standard spi commands: 1. during the ddr dual i/o read command sequence, if the mode bits are not complementary the next time cs# is raised high and then asserted low the device will be released from ddr dual i/o read mode. 2. during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0 and io1) are not set for a valid instruction sequence, then the device will be released from ddr dual i/o read mode. cs# sck si so phase 7 6 5 4 3 2 1 0 3 . 1 0 7 6 5 4 3 2 1 0 7 6 instruction address dummy data 1 d2
january 8, 2014 S25FL512S_00_07 S25FL512S 101 data sheet the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. the hold function is not valid during dual i/o ddr commands. note that the memory devices may drive the ios with a pr eamble prior to the first data value. the preamble is a data learning pattern (dlp) that is used by the ho st controller to optimize data capture at higher frequencies. the preamble dlp drives the io bus for the four clock cycles immediately before data is output. the host must be sure to stop driving the io bus prior to the time that the memo ry starts outputting the preamble. the preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. the host controller will skew the data capture point during the pr eamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. the optimized capture point will be determined during the preamble period of every read oper ation. this optimization strategy is intended to compensate for both the pvt (process, voltage, temperature) of both the memory device and the host controller as well as any syst em level delays caused by flight time on the pcb. although the data learning pattern (dlp) is programma ble, the following example shows example of the dlp of 34h. the dlp 34h (or 00110100) will be driven on eac h of the active outputs (i.e. all four sios on a x4 device, both sios on a x2 device and the single so output on a x1 device). this pattern was chosen to cover both dc and ac data transition scenari os. the two dc transition scenarios include data low for a long period of time (two half clocks) followed by a high going tr ansition (001) and the comple mentary low going transition (110). the two ac transition scenarios include data low for a short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). the dc transitions will typically occur with a starting point cl oser to the supply rail than the ac transitions that may not have fully settled to their steady state (dc) levels. in many case s the dc transitions will bound the beginning of the data valid period and the ac transitions will bound the ending of the data valid period. these transitions will allow the host controller to identify the beginning and ending of the valid data eye. once the data eye has been characterized the optimal data capture point can be chosen. see section 8.6.11, spi ddr data learning registers on page 64 for more details. figure 10.44 ddr dual i/o read initial access (4-byte address, beh or bdh [extadd=1], ehplc= 01b) figure 10.45 continuous ddr dual i/o read subsequent access (4-byte address, ehplc= 01b) cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 28 0 6 4 2 0 7 6 5 4 3 2 1 0 6 4 2 0 6 31 29 1 7 5 3 1 7 6 5 4 3 2 1 0 7 5 3 1 7 instruction address mode dum dlp data 1 cs# sck io0 io1 phase 30 2 0 6 4 2 0 7 6 4 5 3 2 1 0 6 4 2 0 6 31 3 1 7 5 3 1 7 6 4 5 3 2 1 0 7 5 3 1 7 address mode dummy dlp data 1 d2
102 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.46 ddr dual i/o read (4-byte address, beh or bdh [extadd=1], hplc=00b) 10.4.9 ddr quad i /o read (edh, eeh) the read ddr quad i/o command improves throughput with four i/o signals - io0-io3. it is similar to the quad i/o read command but allows input of the address four bits on every edge of the clock. in some applications, the reduced in struction overhead might allow for co de execution (xip) directly from the S25FL512S device. the quad bit of the configuration register must be set (cr bit1=1) to enable the quad capability. the instruction ? edh (extadd=0) is followed by a 3-byte address (a23-a0) or ? edh (extadd=1) is followed by a 4-byte address (a31-a0) or ? eeh is followed by a 4-byte address (a31-a0) the address is followed by mode bits. then the memory c ontents, at the address given, is shifted out, in a ddr fashion, with four bits at a ti me on each clock edge through io0-io3. the maximum operating clock frequency for read ddr quad i/o command is 66 mhz. for read ddr quad i/o, there is a latency required after the last address and mode bits are shifted into the io0-io3 signals before data begins sh ifting out of io0-io3. this latenc y period (dummy cycles) allows the device?s internal circuitry enough ti me to access the initia l address. during these latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. when the data learning pattern (dlp) is enabled the host system must not drive the io signals during the dummy cycles. the io signals must be left high impedance by the host so that the memory device can drive the dlp during the dummy cycles. there are different ordering part numbers that select the latency code table used for this command, either the high performance lc (hplc) table or the enhanced hig h performance lc (ehplc) table. the number of dummy cycles is determined by the frequency of sck (refer to table 8.6, latency codes for ddr high performance on page 59 ). the number of dummy cycles is set by t he lc bits in the c onfiguration register (cr1). both latency tables provide cycles for mode bits so a series of quad i/o ddr commands may eliminate the 8 bit instruction after the first command sends a complementary mode bit pattern, as shown in figure 10.47 and figure 10.49 . this feature removes the need for the eight bit sdr instruction sequence and dramatically reduces initial access times (improves xip performance) . the mode bits control the length of the next read ddr quad i/o operation through the inclusion or exclusion of the first byte instruction code. if the upper nibble (io[7:4]) and lower nibble (io[ 3:0]) of the mode bits are complem entary (i.e. 5h and ah) the device transitions to continuous read ddr quad i/o mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the edh or eeh instruction, as shown in figure 10.48 on page 104 and figure 10.50 on page 104 thus, eliminating eight cycles from the command sequence. the following sequences will release the device from cont inuous read ddr quad i/o mode; after which, the device can accept standard spi commands: 1. during the read ddr quad i/o command sequence, if the mode bits are not complementary the next time cs# is raised high and then asserted low the device will be released from read ddr quad i/o mode. 2. during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0, io1, io2, and io3) are not set for a vali d instruction sequence, then the device will be released from read ddr quad i/o mode. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 31 3 1 7 5 3 1 7 instruction address dummy data 1 d2
january 8, 2014 S25FL512S_00_07 S25FL512S 103 data sheet the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. the hold function is not valid during quad i/o ddr commands. note that the memory devices drive the ios with a preamb le prior to the first data value. the preamble is a pattern that is used by the host controller to optimiz e data capture at higher fre quencies. the preamble drives the io bus for the four clock cycles immediately before data is output. t he host must be sure to stop driving the io bus prior to the time that the memory starts outputting the preamble. the preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. the host controller will skew the data capture point during the pr eamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. the optimized capture point will be determined during the preamble period of every read oper ation. this optimization strategy is intended to compensate for both the pvt (process, voltage, temperature) of both the memory device and the host controller as well as any syst em level delays caused by flight time on the pcb. although the data learning pattern (dlp) is programma ble, the following example shows example of the dlp of 34h. the dlp 34h (or 00110100) will be driven on eac h of the active outputs (i.e. all four sios on a x4 device, both sios on a x2 device and the single so output on a x1 device). this pattern was chosen to cover both dc and ac data transition scenari os. the two dc transition scenarios include data low for a long period of time (two half clocks) followed by a high going tr ansition (001) and the comple mentary low going transition (110). the two ac transition scenarios include data low for a short period of time (one half clock) followed by a high going transition (101) and the complementary low going transition (010). the dc transitions will typically occur with a starting point cl oser to the supply rail than the ac transitions that may not have fully settled to their steady state (dc) levels. in many case s the dc transitions will bound the beginning of the data valid period and the ac transitions will bound the ending of the data valid period. these transitions will allow the host controller to identify the beginning and ending of the valid data eye. once the data eye has been characterized the optimal data capture point can be chosen. see spi ddr data learning registers on page 64 for more details. figure 10.47 ddr quad i/o read initial access (3-byte address, edh [extadd=0], hplc=11b) cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2
104 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.48 continuous ddr quad i/o read subsequent access (3-byte address,hplc=11b) figure 10.49 ddr quad i/o read initial access (4-byte address, eeh or edh [extadd=1], ehplc=01b) note: 1. example dlp of 34h (or 00110100). figure 10.50 continuous ddr quad i/o read subsequent access (4-byte address, ehplc=01b) note: 1. example dlp of 34h (or 00110100). 10.5 program flash array commands 10.5.1 program granularity 10.5.1.1 page programming page programming is done by loading a page buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory a rray. this sets an upper limit on the amount of data that can be programmed with a single programming command. page programming allows up to a page size (512 bytes) to be programmed in one operation. the p age is aligned on the page size address boundary. it is possible to program from one bit up to a page size in each page programming operation. it is recommended that a multiple of 16 byte length and aligned progra m blocks be written. for the very best performance, programming should be done in full pages of 512 by tes aligned on 512-byte boundaries with each page being programmed only once. cs# sck io0 io1 io2 io3 phase 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 address mode dummy d1 d2 d3 d4 d5 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 2 . 2 . 2 . 1. 1. 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 2 . 2 . 2 . 1. 1. 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 3 . 2 . 2 . 1. 1. 1. 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 3 . 2 . 2 . 1. 1. 1. 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mod . dummy dlp d1 d2 cs# sck io0 io1 io2 io3 phase 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 4 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 5 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 6 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 7 address mode dummy dlp d1 d2
january 8, 2014 S25FL512S_00_07 S25FL512S 105 data sheet 10.5.1.2 single byte programming single byte programming allows full backward compat ibility to the standard spi page programming (pp) command by allowing a single byte to be programmed anywhere in the memory array. 10.5.2 page program (p p 02h or 4pp 12h): the page program (pp) commands allows bytes to be pr ogrammed in the memory (changing bits from 1 to 0). before the page program (pp) commands can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device sets the write enable lat ch (wel) in the status register to enable any write operations. the instruction ? 02h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 02h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 12h is followed by a 4-byte address (a31-a0) and at least one data byte on si. up to a page can be provided on si after the 3-byte address with instruction 02h or 4-byte address with instruction 12h has been prov ided. if the 9 least significant address bits (a8-a0) are not all zero, all transmitted data that goes beyond the end of the curr ent page are programmed from the start address of the same page (from the address whose 9 least significant bits (a8-a0) are all zero) i.e. the address wraps within the page aligned address boundaries. this is a result of only requiring the user to enter one single page address to cover the entire page boundary. if less than a page of data is sent to the device, thes e data bytes will be programmed in sequence, starting at the provided address within the page, without having any affect on the other bytes of the same page. for optimized timings, using the page program (pp) comm and to load the entire page size program buffer within the page boundary will save overall programming time versus loading less than a page size into the program buffer. the programming process is managed by the flash memory device internal control logic. after a programming command is issued, the programming operation status ca n be checked using the read status register-1 command. the wip bit (sr1[0]) will indicate when th e programming operation is completed. the p_err bit (sr1[6]) will indicate if an error occurs in the prog ramming operation that prevents successful completion of programming. figure 10.51 page program (pp 02h or 4pp 12h) command sequence 10.5.3 quad page program (q pp 32h or 38h, or 4qpp 34h) the quad-input page program (qpp) command allows bytes to be programmed in the memory (changing bits from 1 to 0). the quad-input page program (qpp) co mmand allows up to a page size (512 bytes) of data to be loaded into the page buffer using four sign als: io0-io3. qpp can improve performance for prom programmer and applications that have slower clock s peeds (< 12 mhz) by loading 4 bits of data per clock cycle. systems with faster clock sp eeds do not realize as much benefit for the qpp command since the inherent page program time becomes greater than the time it takes to clock-in the data. the maximum frequency for the qpp command is 80 mhz. cs# sck si so phase 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2
106 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet to use quad page program the quad enable bit in th e configuration register must be set (quad=1). a write enable command must be executed before the device will accept the qpp command (status register- 1, wel=1). the instruction ? 32h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 32h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 38h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 38h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 34h is followed by a 4-byte address (a31-a0) and at least one data byte, into the io signals. data must be programmed at previously erased (ffh) memory locations. qpp requires programming to be done one full page at a time. while less than a full page of data may be loaded for programming, the entire page is consider ed programmed, any locations not filled with data will be left as ones, the same page must not be programmed more than once. all other functions of qpp are identical to page program. the qpp command sequence is shown in the figure below. figure 10.52 quad 512-byte page program command sequence 10.5.4 program suspend (pgsp 85h) and resume (pgrs 8ah) the program suspend command allows the system to inte rrupt a programming opera tion and then read from any other non-erase-suspended sector or non-prog ram-suspended-page. program suspend is valid only during a programming operation. commands allowed after the progr am suspend command is issued: ? read status register 1 (rdsr1 05h) ? read status register 2 (rdsr2 07h) the write in progress (wip) bit in status register 1 (sr1[0]) must be checked to know when the programming operation has stopped. the program suspend status bit in the status register-2 (sr2[0]) can be used to determine if a programming operation ha s been suspended or was completed at the time wip changes to 0. the time required for the suspend operation to complete is t psl , see table 10.8, program suspend ac parameters on page 118 . see table 10.6, commands allowed during program or erase suspend on page 110 for the commands allowed while programming is suspend. the program resume command 8ah must be written to resume the programming operation after a program suspend. if the programming operation was completed during the suspend operatio n, a resume command is not needed and has no effect if issued. program resume commands will be ignored unless a program operation is suspended. after a program resume command is i ssued, the wip bit in the status register-1 will be set to a 1 and the programming operation will resume. program operations may be interrupted as often as necessary e.g. a program suspend command could immediately follow a program resume command but, in order for a cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 a 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address data 1 data 2 data 3 data 4 data 5 ...
january 8, 2014 S25FL512S_00_07 S25FL512S 107 data sheet program operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t prs . see table 10.8, program suspend ac parameters on page 118 . figure 10.53 program suspend (pgsp 85h) command sequence figure 10.54 10.55 program resume (pgrs 8ah) command sequence 10.6 erase flash array commands 10.6.1 sector erase (se d8h or 4se dch): the sector erase (se) command sets all bits in the ad dressed sector to 1 (all bytes are ffh). before the sector erase (se) command can be accepted by th e device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? d8h [extadd=0] is followed by a 3-byte address (a23-a0), or ? d8h [extadd=1] is followed by a 4-byte address (a31-a0), or ? dch is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high state after t he twenty-fourth or thirty-s econd bit of address has been latched in on si. this will initiate the erase cycle, which involves the pre-programming and erase of the chosen sector. if cs# is not driven high after the last bit of address, the sector erase operation will not be executed. as soon as cs# is driven into the logic high state, t he internal erase cycle will be in itiated. with the internal erase cycle in progress, the user can read the value of the write-in progress (w ip) bit to check if the operation has been completed. the wip bit will in dicate a 1 when the erase cycle is in progress and a0 when the erase cycle has been completed. a sector erase (se) command applied to a sector that has been write protected th rough the block protection bits or asp, will not be executed and will set the e_err status. asp has a ppb and a dyb protection bit for each sector. cs# sck si so phase phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 suspend instruction read status instruction status instr. during suspend repeat status read until suspended tpsl cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
108 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.55 sector erase (se d8h or 4se dch) command sequence 10.6.2 bulk erase (be 60h or c7h): the bulk erase (be) command sets all bits to 1 (all bytes are ffh) inside the entire flash memory array. before the be command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. this will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory array. if cs# is not driven high after the last bit of instruction, the be operation will not be executed. as soon as cs# is driven into the logic high state, the erase cycle will be initiat ed. with the erase cycle in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. a be command can be executed only when the block protecti on (bp2, bp1, bp0) bits are set to 0?s. if the bp bits are not zero, the be command is not executed and e_err is not set. the be command will skip any sectors protected by the dyb or ppb and the e_err status will not be set. figure 10.56 bulk erase command sequence 10.6.3 erase suspend and resume co mmands (ersp 75h or errs 7ah) the erase suspend comm and, allows the system to inte rrupt a sector erase operation and then read from or program data to, any other sector. erase suspend is va lid only during a sector erase operation. the erase suspend command is ignored if writte n during the bulk erase operation. when the erase suspend command is written during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation and update the status bits. see table 10.9, erase suspend ac parameters on page 118 . commands allowed after the erase suspend command is issued: ? read status register 1 (rdsr1 05h) ? read status register 2 (rdsr2 07h) the write in progress (wip) bit in st atus register 1 (sr1[0]) must be checked to know when the erase operation has stopped. the erase suspend bit in status register-2 (sr2[1]) can be used to determine if an erase operation has been suspended or was completed at the time wip changes to 0. if the erase operation was completed during the suspend operation, a resume command is not needed and has no effect if issued. erase resume commands w ill be ignored unless an erase operation is suspended. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sck si so phase 76543210 instruction
january 8, 2014 S25FL512S_00_07 S25FL512S 109 data sheet see table 10.6, commands allowed during program or erase suspend on page 110 for the commands allowed while erase is suspend. after the erase operation has been suspended, the se ctor enters the erase-suspend mode. the system can read data from or program data to the device. r eading at any address within an erase-suspended sector produces undetermined data. a wren command is required before any command that will change non-volatile data, even during erase suspend. the wrr and ppb erase commands are not allowed during erase suspend, it is t herefore not possible to alter the block protection or ppb bi ts during erase suspend. if there are sectors that may need programming during erase suspend, these sectors should be protected only by dyb bits that can be turned off during erase suspend. however, wrr is allowed immediatel y following the brac command; in this special case the wrr is interpreted as a write to the bank address register, not a write to sr1 or cr1. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. after an erase-suspended program operation is complete , the device returns to the erase-suspend mode. the system can determine the status of the program operat ion by reading the wip bit in the status register, just as in the standard program operation. the erase resume command 7ah must be written to resu me the erase operation if an erase is suspend. erase resume commands will be ignored unless an erase is suspend. after an erase resume command is sent, the wip bit in the status register will be set to a 1 and the erase operation will continue. further resume commands are ignored. erase operations may be interrupted as often as necessary e.g. an erase suspend command could immediately follow an erase resume command but, in order for an erase operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t ers . see table 10.9, erase suspend ac parameters on page 118 . figure 10.57 erase suspend (ersp 75h) command sequence figure 10.58 erase resume (errs 7ah) command sequence cs# sck si so phase phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 suspend instruction read status instruction status instr. during suspend repeat status read until suspended tesl cs# sck si so phase 76543210 instruction
110 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet table 10.6 commands allowed during program or erase suspend instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment brac b9 x x bank address register may need to be changed during a suspend to reach a sector for read or program. brrd 16 x x bank address register may need to be changed during a suspend to reach a sector for read or program. brwr 17 x x bank address register may need to be changed during a suspend to reach a sector for read or program. clsr 30 x clear status may be used if a program operation fails during erase suspend. dybrd e0 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. dybwr e1 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. errs 7a x required to resume from erase suspend. ddrfr 0d x x all array reads allowed in suspend. 4ddrfr 0e x x all array reads allowed in suspend. fast_read 0b x x all array reads allowed in suspend. 4fast_read 0c x x all array reads allowed in suspend. mbr ff x x may need to reset a read operation during suspend. pgrs 8a x x needed to resume a program operation. a program resume may also be used during nested program suspend within an erase suspend. pgsp 85 x program suspend allowed during erase suspend. pp 02 x required for array program during erase suspend. 4pp 12 x required for array program during erase suspend. ppbrd e2 x allowed for checking persistent protection before attempting a program command during erase suspend. qpp 32, 38 x required for array program during erase suspend. 4qpp 34 x required for array program during erase suspend. 4read 13 x x all array reads allowed in suspend. rdcr 35 x x dior bb x x all array reads allowed in suspend. 4dior bc x x all array reads allowed in suspend. dor 3b x x all array reads allowed in suspend. 4dor 3c x x all array reads allowed in suspend. ddrdior bd x x all array reads allowed in suspend. 4ddrdior be x x all array reads allowed in suspend. ddrqior ed x x all array reads allowed in suspend. ddrqior4 ee x x all array reads allowed in suspend. qior eb x x all array reads allowed in suspend. 4qior ec x x all array reads allowed in suspend. qor 6b x x all array reads allowed in suspend. 4qor 6c x x all array reads allowed in suspend. rdsr1 05 x x needed to read wip to determine end of suspend process. rdsr2 07 x x needed to read suspend status to determine whether the operation is suspended or complete. read 03 x x all array reads allowed in suspend. reset f0 x x reset allowed anytime. wren 06 x required for program command within erase suspend. wrr 01 x x bank register may need to be changed during a suspend to reach a sector needed for read or program. wrr is allowed when following brac.
january 8, 2014 S25FL512S_00_07 S25FL512S 111 data sheet 10.7 one time program array commands 10.7.1 otp program (otpp 42h): the otp program command programs data in the one time program region, which is in a different address space from the main array data. the otp region is 1024 bytes so, the address bits from a23 to a10 must be zero for this command. refer to section 8.5, otp address space on page 55 for details on the otp region. the protocol of the otp program command is the same as the page program command. before the otp program command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the st atus register to enable any write operations. to program the otp array in bit granularity, the rest of the bits within a data byte can be set to 1. each region in the otp memory space can be programm ed one or more times, provided that the region is not locked. attempting to program zeros in a region that is locked will fail with the p_err bit in sr1 set to 1 programming ones, even in a protected area does not cause an error and does not set p_err. subsequent otp programming can be performed only on th e un-programmed bits (that is, 1 data). figure 10.59 page program (otpp 42h) command sequence 10.7.2 otp read (otpr 4bh): the otp read command reads data from the otp region. the otp region is 1024 bytes so, the address bits from a23 to a10 must be zero for this command. refer to otp address space on page 55 for details on the otp region. the protocol of the otp read command is si milar to the fast read command except that it will not wrap to the starting address af ter the otp address is at its maximu m; instead, the data beyond the maximum otp address will be undefined. also, the otp read command is not affected by the latency code. the otp read command always has one dummy byte of latency as shown below. figure 10.60 read otp (otpr 4bh) command sequence 10.8 advanced sector protection commands 10.8.1 asp r ead (asprd 2bh) the asp read instruction 2bh is shifted into si by the rising edge of the sck signal. then the 16-bit asp register contents is shifted ou t on the serial output so, le ast significant byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the asp register continuously by providing multiples of 16 clock cycles. the maximu m operating clock frequency for the asp read (asprd) command is 133 mhz. cs# sck si so phase 7 6 5 4 3 2 1 0 23 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
112 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet figure 10.61 asprd command 10.8.2 asp program (aspp 2fh) before the asp program (aspp) command can be a ccepted by the device, a write enable (wren) command must be issued. after the write enable (w ren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the aspp command is entered by driving cs# to the logic low state, followed by the instruction and two data bytes on si, least significant byte first. the asp register is two data bytes in length. the aspp command affects the p_err and wip bits of the status an d configuration regi sters in the same manner as any other programming operation. cs# input must be driven to the logic high state after th e sixteenth bit of data has been latched in. if not, the aspp command is not executed. as soon as cs# is dr iven to the logic high st ate, the self-timed aspp operation is initiated. while the aspp operation is in progress, the status register may be read to check the value of the write-in progress (wip ) bit. the write-in pr ogress (wip) bit is a 1 during the self-timed aspp operation, and is a 0 when it is completed. when t he aspp operation is completed, the write enable latch (wel) is set to a 0. figure 10.62 aspp (2fh) command 10.8.3 dyb read (dybrd e0h) the instruction e0h is latched into si by the rising edg e of the sck signal. follow ed by the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used by a particular density device must be zero). then the 8-bit dyb access register content s are shifted out on the serial output so. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the same dyb access register contin uously by providing multiples of ei ght clock cycles. the address of the dyb register does not increment so this is not a means to read the entire dyb array. each location must be read with a separate dyb read command. the maximum operating clock frequency for read command is 133 mhz. figure 10.63 dybrd command sequence cs# sck si so phase 76543210 7654321076543210 instruction register read repeat register read cs# sck si so phase 765432107654321076543210 instruction input aspr low byte input aspr high byte cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address register repeat register
january 8, 2014 S25FL512S_00_07 S25FL512S 113 data sheet 10.8.4 dyb write (dybwr e1h) before the dyb write (dybwr) command can be accept ed by the device, a write enable (wren) command must be issued. after the write enable (wren) comm and has been decoded, the device will set the write enable latch (wel) in the status regi ster to enable any write operations. the dybwr command is entered by driving cs# to the logi c low state, followed by the instruction, the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used by a particular density device must be zero), then the data byte on si. the dyb access register is one data byte in length. the dybwr command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# must be driven to the logic high state after the eighth bit of data has been latched in. if not, the dybwr comman d is not executed. as soon as cs# is driven to the logic high state, the self-timed dybw r operation is initiated. while the dybwr operation is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed dybwr operation, and is a 0 when it is completed. when the dybwr operation is completed, the write enable latch (wel) is set to a 0. figure 10.64 dybwr (e1h) command sequence 10.8.5 ppb r ead (ppbrd e2h) the instruction e2h is shifted into si by the rising edges of the sck signal, followed by the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used by a particular density device must be zero) th en the 8-bit ppb access register contents are sh ifted out on so. it is possible to read the same ppb access register continuously by providing multiples of eight clock cycles. the address of the ppb r egister does not increment so this is not a means to read the entire ppb array. each location must be read with a separate ppb read command. the maximum operating clock frequency for the ppb read command is 133 mhz. figure 10.65 ppbrd (e2h) command sequence 10.8.6 ppb program (ppbp e3h) before the ppb program (ppbp) command can be a ccepted by the device, a write enable (wren) command must be issued. after the write enable (w ren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the ppbp command is entered by driving cs# to the logic low state, followed by the instruction, followed by the 32-bit address selecting location ze ro within the desired sector (note, the high order address bits not used by a particular density device must be zero). cs# sck si so phase 7654321031 54321076543210 instruction address input data cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address register repeat register
114 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet the ppbp command affects the p_err and wip bits of the status an d configuration regi sters in the same manner as any other programming operation. cs# must be driven to the logic high state after the last bit of addre ss has been latched in . if not, the ppbp command is not executed. as soon as cs# is driven to the logic high state, the self-timed ppbp operation is initiated. while the ppbp operation is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the wr ite-in progress (wip) bit is a 1 du ring the self-timed ppbp operation, and is a 0 when it is completed. when the ppbp operation is comple ted, the write enable latch (wel) is set to a 0. figure 10.66 ppbp (e3h) command sequence 10.8.7 ppb erase (ppbe e4h) the ppb erase (ppbe) command sets al l ppb bits to 1. before the ppb erase command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction e4h is shifted into si by the rising edges of the sck signal. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. this will initiate the beginning of internal erase cycle, which involves the pre-prog ramming and erase of the entire ppb memory array. without cs# being driven to the logic high state afte r the eighth bit of the instruction, the ppb erase o peration will not be executed. with the internal erase cycle in progress, the user can read the value of the writ e-in progress (wip) bit to check if the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. eras e suspend is not allowed during ppb erase. figure 10.67 ppb erase (ppbe e4h) command sequence 10.8.8 ppb lock bit read (plbrd a7h) the ppb lock bit read (plbrd) command allows the ppb lock register contents to be read out of so. it is possible to read the ppb lock register continuously by providing multiple s of eight clock cycles. the ppb lock register contents may only be read when the device is in standby state with no othe r operation in progress. it is recommended to check the write-in progress (wip) bit of the status register before issuing a new command to the device. cs# sck si so phase 7 6 5 4 3 2 1 0 31 1 0 instruction address cs# sck si so phase 76543210 instruction
january 8, 2014 S25FL512S_00_07 S25FL512S 115 data sheet figure 10.68 ppb lock register read command sequence 10.8.9 ppb lock bit write (plbwr a6h) the ppb lock bit write (plbwr) command clears the ppb lock regist er to zero. before the plbwr command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the plbwr command is entered by driving cs# to the logic low state, followed by the instruction. cs# must be driven to the logic high state after the ei ghth bit of instruction has been latched in. if not, the plbwr command is not executed. as soon as cs# is dr iven to the logic high st ate, the self-timed plbwr operation is initiated. while the plbwr operation is in progress, the status regist er may still be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed plbwr operation, and is a 0 when it is completed. when the plbwr operation is completed, the write enable latch (wel) is set to a 0. the maximu m clock frequency for the plbwr command is 133 mhz. figure 10.69 ppb lock bit write (plbwr a6h) command sequence 10.8.10 password read (passrd e7h) the correct password value may be read only after it is programmed and before the password mode has been selected by programming t he password protection mode bit to 0 in the asp register (asp[2]). after the password protection mode is select ed the passrd command is ignored. the passrd command is shifted into si . then the 64-bit password is shifted out on the serial output so, least significant byte first, most signific ant bit of each byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to re ad the password continuously by providing multiples of 64 clock cycles. the maximum operating clock fr equency for the passrd command is 133 mhz. figure 10.70 password read (passrd e7 h) command sequence 10.8.11 password program (passp e8h) before the password program (passp) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded, the device sets the write enable latch (wel) to enable the passp operation. cs# sck si so phase 76543210 7654321076543210 instruction register read repeat register read cs# sck si so phase 76543210 instruction cs# sck si so phase 76543210 7654321076543210 instruction data 1 data n
116 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet the password can only be programmed before the password mode is selected by programming the password protection mode bit to 0 in the asp register (asp[2]). afte r the password protection mode is selected the passp co mmand is ignored. the passp command is entered by driving cs# to the l ogic low state, followed by the instruction and the password data bytes on si, least signif icant byte first, most significant bit of each byte first. the password is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passp command is not executed. as soon as cs# is driven to the logic high st ate, the self-timed passp operation is initiated. while the passp operation is in progress, the status regi ster may be read to check the value of the write-in progress (wip ) bit. the write-in pr ogress (wip) bit is a 1 during the self-timed passp cycle, and is a 0 when it is comple ted. the passp command can report a program error in the p_err bit of the status register. when the passp ope ration is completed, the write enable latch (wel ) is set to a 0. the maximum clock frequency for the passp command is 133 mhz. figure 10.71 password program (passp e8h) command sequence 10.8.12 password unlock (passu e9h) the passu command is entered by dr iving cs# to the logic low state, followed by the instruction and the password data bytes on si, least signif icant byte first, most significant bit of each byte first. the password is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passu command is not executed. as soon as cs# is dr iven to the logic high state, the self-timed passu operation is initiated. while the passu operation is in progress, the status register may be read to check the value of the write-in progress (wip ) bit. the write-in pr ogress (wip) bit is a 1 during the self-timed passu cycle, and is a 0 when it is completed. if the passu command supplied password does not ma tch the hidden password in the password register, an error is reported by setting the p_err bit to 1. the wip bit of the status register also remains set to 1. it is necessary to use the clsr command to clear the status regi ster, the reset command to software reset the device, or drive the reset# input low to initiate a hardware reset, in orde r to return the p_err and wip bits to 0. this returns the device to standby state, ready for new commands such as a retry of the passu command. if the password does match, the ppb lock bit is set to 1. the ma ximum clock frequency for the passu command is 133 mhz. figure 10.72 password unlock (passu e9h) command sequence cs# sck si so phase 765432107654321076543210 instruction input password low byte input password high byte cs# sck si so phase 765432107654321076543210 instruction input password low byte input password high byte
january 8, 2014 S25FL512S_00_07 S25FL512S 117 data sheet 10.9 reset commands 10.9.1 software reset command (reset f0h) the software reset command (reset) restores the device to its initial power up state, except for the volatile freeze bit in the configur ation register cr1[1 ] and the volatile ppb lock bit in the ppb lock register. the freeze bit and the ppb lock bit will rema in set at their last value prior to the software reset. to clear the freeze bit and set the ppb lock bit to its protection mode selected power on state, a full power-on-reset sequence or hardware reset must be done. note that t he non-volatile bits in t he configuration register, tbprot, tbparm, and bpnv, retain thei r previous state after a software reset. the block protection bits bp2, bp1, and bp0, in the status register will only be rese t if they are configured as volatile via the bpnv bit in the configuration register (cr1[3]) and freeze is cl eared to zero . the software reset cannot be used to circumvent the freeze or ppb lock bi t protection mechanisms fo r the other security configuration bits. the reset command is executed when cs# is brought to high state and requires t rph time to execute. figure 10.73 software reset (reset f0 h) command sequence 10.9.2 mode bit reset (mbr ffh) the mode bit reset (mbr) command can be used to retu rn the device from contin uous high performance read mode back to normal standby awaiting any new command. because some device packages lack a hardware reset# input and a device th at is in a continuous high perfor mance read mode may not recognize any normal spi comma nd, a system hardware reset or software reset command may not be recognized by the device. it is recommended to use the mbr command after a system reset when the reset# signal is not available or, before sending a software reset, to ensure the device is released from continuous high performance read mode. the mbr command sends ones on si or io0 for 8 sc k cycles. io1 to io3 are ?don?t care? during these cycles. figure 10.74 mode bit (mbr ffh) reset command sequence cs# sck si so phase 76543210 instruction cs# sck si so phase 76543210 instruction
118 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 10.10 embedded algorithm performance tables notes: 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0v; 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c; 100,000 cycles max. 3. industrial temperature range / automotive in-cabin temperature range. table 10.7 program and erase performance symbol parameter min typ (1) max (2) unit t w wrr write time 560 2000 ms t pp page programming (512 bytes) 340 750/1300 (3) s t se sector erase time (256-kb logical sectors = 4 x 64 kb physical sectors) 520 2600 ms t be bulk erase time (S25FL512S) 103 460 sec table 10.8 program suspend ac parameters parameter min typical max unit comments program suspend latency (t psl ) 40 s the time from program suspend command until the wip bit is 0 program resume to next program suspend (t prs ) 0.06 100 s minimum is the time needed to issue the next program suspend command but typical periods are needed for program to progress to completion table 10.9 erase suspend ac parameters parameter min typical max unit comments erase suspend latency (t esl ) 45 s the time from erase suspend command until the wip bit is 0 erase resume to next erase suspend (t ers) 0.06 100 s minimum is the time needed to issue the next erase suspend command but typical periods are needed for the erase to progress to completion
january 8, 2014 S25FL512S_00_07 S25FL512S 119 data sheet 11. software interface reference 11.1 command summary table 11.1 S25FL512S instruction set (sorted by instruction) (sheet 1 of 2) instruction (hex) command name command description maximum frequency (mhz) 01 wrr write register (status-1, configuration-1) 133 02 pp page program (3- or 4-byte address) 133 03 read read (3- or 4-byte address) 50 04 wrdi write disable 133 05 rdsr1 read status register-1 133 06 wren write enable 133 07 rdsr2 read status register-2 133 0b fast_read fast read (3- or 4-byte address) 133 0c 4fast_read fast read (4-byte address) 133 0d ddrfr ddr fast read (3- or 4-byte address) 66 0e 4ddrfr ddr fast read (4-byte address) 66 12 4pp page program (4-byte address) 133 13 4read read (4-byte address) 50 14 abrd autoboot register read 133 15 abwr autoboot register write 133 16 brrd bank register read 133 17 brwr bank register write 133 18 reserved-18 reserved 2b asprd asp read 133 2f aspp asp program 133 30 clsr clear status register - erase/program fail reset 133 32 qpp quad page program (3- or 4-byte address) 80 34 4qpp quad page program (4-byte address) 80 35 rdcr read configuration register-1 133 38 qpp quad page program (3- or 4-byte address) 80 3b dor read dual out (3- or 4-byte address) 104 3c 4dor read dual out (4-byte address) 104 41 dlprd data learning pattern read 133 42 otpp otp program 133 43 pnvdlr program nv data learning register 133 4a wvdlr write volatile data learning register 133 4b otpr otp read 133 5a rsfdp read serial flash discoverable parameters 133 60 be bulk erase 133 6b qor read quad out (3- or 4-byte address) 104 6c 4qor read quad out (4-byte address) 104 75 ersp erase suspend 133 7a errs erase resume 133 85 pgsp program suspend 133 8a pgrs program resume 133 90 read_id (rems) read electronic manufacturer signature 133 9f rdid read id (jedec manufacturer id and jedec cfi) 133 a3 mpm reserved for multi-i/o-high perf mode (mpm) 133 a6 plbwr ppb lock bit write 133
120 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 11.2 serial flash discoverable pa rameters (sfdp) address map the sfdp address space has a header starting at address zero that identifies the sfdp data structure and provides a pointer to each parameter. one paramet er is mandated by the jedec jesd216 standard. spansion provides an additional parameter by pointing to the id-cfi address space i.e. the id-cfi address space is a sub-set of the sfdp a ddress space. the jedec parameter is located within the id-cfi address space and is thus both a cfi parameter and an sfdp parameter. in this way both sfdp and id-cfi information can be accessed by either the rsfdp or rdid commands. a7 plbrd ppb lock bit read 133 ab res read electronic signature 50 b9 brac bank register access (legacy command formerly used for deep power down) 133 bb dior dual i/o read (3- or 4-byte address) 104 bc 4dior dual i/o read (4-byte address) 104 bd ddrdior ddr dual i/o read (3- or 4-byte address) 66 be 4ddrdior ddr dual i/o read (4-byte address) 66 c7 be bulk erase (alternate command) 133 d8 se erase 256 kb (3- or 4-byte address) 133 dc 4se erase 256 kb (4-byte address) 133 e0 dybrd dyb read 133 e1 dybwr dyb write 133 e2 ppbrd ppb read 133 e3 ppbp ppb program 133 e4 ppbe ppb erase 133 e5 reserved-e5 reserved e6 reserved-e6 reserved e7 passrd password read 133 e8 passp password program 133 e9 passu password unlock 133 eb qior quad i/o read (3- or 4-byte address) 104 ec 4qior quad i/o read (4-byte address) 104 ed ddrqior ddr quad i/o read (3- or 4-byte address) 66 ee 4ddrqior ddr quad i/o read (4-byte address) 66 f0 reset software reset 133 ff mbr mode bit reset 133 table 11.1 S25FL512S instruction set (sorted by instruction) (sheet 2 of 2) instruction (hex) command name command description maximum frequency (mhz) table 11.2 sfdp overview map relative byte address offset sfdp dword address description 0000h 00h location zero within sfdp space - start of sfdp header ,,, ... remainder of sfdp header followed by undefined space 1000h 400h location zero within id-cfi space - start of id-cfi ... ... id-cfi parameters 1120h 448h start of sfdp jedec parameter which is also part of a cfi parameter ... ... remainder of sfdp jedec parameter followed by either more cfi parameters or undefined space
january 8, 2014 S25FL512S_00_07 S25FL512S 121 data sheet 11.2.1 field definitions table 11.3 sfdp header relative byte address offset sfdp dword address data description 00h 00h 53h this is the entry point for read sfdp (5ah ) command i.e. location zero within sfdp space ascii ?s? 01h 46h ascii ?f? 02h 44h ascii ?d? 03h 50h ascii ?p? 04h 01h 00h sfdp minor revision 05h 01h sfdp major revision 06h 01h number of parameter headers (zero based, 01h = 2 parameters) 07h ffh unused 08h 02h 00h manufacturer id (jedec sfdp mandatory parameter) 09h 00h parameter minor revision 0ah 01h parameter major revision 0bh 09h parameter table length (in double words = dwords = 4 byte units) 0ch 03h 48h parameter table pointer byte 0 (dword = 4 byte aligned) jedec parameter byte offset = 1120h = 448h dword address 0dh 04h parameter table pointer byte 1 0eh 00h parameter table pointer byte 2 0fh ffh unused 10h 04h 01h manufacturer id (spansion) 11h 00h parameter minor revision 12h 01h parameter major revision 13h 51h parameter table length (in double words = dwords = 4 byte units) 14h 05h 00h parameter table pointer byte 0 (dword = 4 byte aligned) entry point for id-cfi parameter is byte offset = 1000h relative to sfdp location zero. 1000h bytes = 400h dwords 15h 04h parameter table pointer byte 1 16h 00h parameter table pointer byte 2 17h ffh unused
122 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 11.3 device id and common flash in terface (id-cfi) address map 11.3.1 field definitions table 11.4 manufacturer and device id byte address data description 00h 01h manufacturer id for spansion 01h 02h (512 mb) device id most significant byte - memory interface type 02h 20h (512 mb) device id least significant byte - density 03h xxh id-cfi length - number bytes following. adding this value to the current location of 03h gives the address of the last valid location in the id-cfi address map. a value of 00h indicates the entire 512-byte id-cfi space must be read because the actual length of the id-cfi information is longer than can be indicated by this legacy single byte field. the value is opn dependent. 04h 00h (uniform 256-kb sectors) sector architecture 05h 80h (fl-s family) family id 06h xxh ascii characters for model refer to ordering information on page 137 for the model number definitions. 07h xxh 08h xxh reserved 09h xxh reserved 0ah xxh reserved 0bh xxh reserved 0ch xxh reserved 0dh xxh reserved 0eh xxh reserved 0fh xxh reserved table 11.5 cfi query identification string byte address data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set fl-p backward compatible command set id 15h 16h 40h 00h address for primary extended table 17h 18h 53h 46h alternate oem command set ascii characters ?fs? for spi (f) interface, s technology 19h 1ah 51h 00h address for alternate oem extended table
january 8, 2014 S25FL512S_00_07 S25FL512S 123 data sheet table 11.6 cfi system interface string byte address data description 1bh 27h v cc min. (erase/program): 100 millivolts 1ch 36h v cc max. (erase/program): 100 millivolts 1dh 00h v pp min. voltage (00h = no v pp present) 1eh 00h v pp max. voltage (00h = no v pp present) 1fh 06h typical timeout per single byte program 2 n s 20h 09h (512b page) typical timeout for min. size page program 2 n s (00h = not supported) 21h 09h (256 kb) typical timeout per individual sector erase 2 n ms 22h 11h (512 mb) typical timeout for full chip erase 2 n ms (00h = not supported) 23h 02h max. timeout for byte program 2 n times typical 24h 02h max. timeout for page program 2 n times typical 25h 03h max. timeout per individual sector erase 2 n times typical 26h 03h max. timeout for full chip erase 2 n times typical (00h = not supported) table 11.7 device geometry definition for 512-mbit device byte address data description 27h 1ah (512 mb) device size = 2 n bytes; 28h 02h flash device interface description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = single i/o spi, 3-byte address 0005h = multi i/o spi, 3-byte address 0102h = multi i/o spi, 3- or 4-byte address 29h 01h 2ah 09h max. number of bytes in multi-byte write = 2 n (0000 = not supported 0009h = 512b page) 2bh 00h 2ch 01h number of erase block regions within device 1 = uniform device, 2 = boot device 2dh ffh erase block region 1 information (refer to jedec jep137) 32 sectors = 32-1 = 001fh 4-kb sectors = 256 bytes x 0010h 2eh 00h 2fh 00h 30h 04h 31h thru 3fh ffh rfu
124 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet table 11.8 cfi primary vendor-specific extended query byte address data description 40h 50h query-unique ascii string ?pri? 41h 52h 42h 49h 43h 31h major version number = 1, ascii 44h 33h minor version number = 3, ascii 45h 21h address sensitive unlock (bits 1-0) 00b = required 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.11 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 1000b = 0.065 m mirrorbit 46h 02h erase suspend 0 = not supported 1 = read only 2 = read and program 47h 01h sector protect 00 = not supported x = number of sectors in group 48h 00h temporary sector unprotect 00 = not supported 01 = supported 49h 08h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method 09 = secure 4ah 00h simultaneous operation 00 = not supported x = number of sectors 4bh 01h burst mode (synchronous sequential read) support 00 = not supported 01 = supported 4ch xxh page mode type, model dependent 00 = not supported 01 = 4 word read page 02 = 8 read word page 03 = 256-byte program page 04 = 512-byte program page 4dh 00h acc (acceleration) supply minimum 00 = not supported, 100 mv 4eh 00h acc (acceleration) supply maximum 00 = not supported, 100 mv 4fh 07h wp# protection 01 = whole chip 04 = uniform device with bottom wp protect 05 = uniform device with top wp protect 07 = uniform device with top or bottom write protect (user select) 50h 01h program suspend 00 = not supported 01 = supported
january 8, 2014 S25FL512S_00_07 S25FL512S 125 data sheet the alternate vendor-specific extended query provid es information related to the expanded command set provided by the fl-s family. the alternate query parameters use a format in which each parameter begins with an identifier byte and a parameter length byte. driver software can check each parameter id and can use the length value to skip to the next parameter if the parameter is not needed or not recognized by the software. table 11.9 cfi alternate vendor-specific extended query header byte address data description 51h 41h query-unique ascii string ?alt? 52h 4ch 53h 54h 54h 32h major version number = 2, ascii 55h 30h minor version number = 0, ascii table 11.10 cfi alternate vendor-specific extended query parameter 0 parameter relative byte address offset data description 00h 00h parameter id (ordering part number) 01h 10h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 53h ascii ?s? for manufacturer (spansion) 03h 32h ascii ?25? for product characters (single die spi) 04h 35h 05h 46h ascii ?fl? for interface characters (spi 3 volt) 06h 4ch 07h 35h (512 mb) ascii characters for density 08h 31h (512 mb) 09h 32h (512 mb) 0ah 53h ascii ?s? for technology (65nm mirrorbit) 0bh xxh reserved for future use (rfu) 0ch xxh 0dh xxh 0eh xxh 0fh xxh 10h xxh 11h xxh table 11.11 cfi alternate vendor-specific extend ed query parameter 80h address options parameter relative byte address offset data description 00h 80h parameter id (ordering part number) 01h 01h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h f0h bits 7:4 - reserved = 1111b bit 3 - autoboot support - ye s= 0b, no = 1b bit 2 - 4-byte address instructions supported - yes = 0b, no = 1b bit 1 - bank address + 3-byte address inst ructions supported - yes = 0b, no = 1b bit 0 - 3-byte address instructions supported - yes = 0b, no = 1b
126 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet table 11.12 cfi alternate vendor-specific extended query parameter 84h suspend commands parameter relative byte address offset data description 00h 84h parameter id (suspend commands 01h 08h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 85h program suspend instruction code 03h 28h program suspend latency maximum (s) 04h 8ah program resume instruction code 05h 64h program resume to next suspend typical (s) 06h 75h erase suspend instruction code 07h 28h erase suspend latency maximum (s) 08h 7ah erase resume instruction code 09h 64h erase resume to ne xt suspend typical (s) table 11.13 cfi alternate vendor-specific extended query parameter 88h data protection parameter relative byte address offset data description 00h 88h parameter id (data protection) 01h 04h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 0ah otp size 2 n bytes, ffh = not supported 03h 01h otp address map format, 01h = fl-s format, ffh = not supported 04h xxh block protect type, model dependent 00h = fl-p, fl-s, ffh = not supported 05h xxh advanced sector protection type, model dependent 01h = fl-s asp table 11.14 cfi alternate vendor-specific extended query parameter 8ch reset timing parameter relative byte address offset data description 00h 8ch parameter id (reset timing) 01h 06h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 96h por maximum value 03h 01h por maximum exponent 2 n s 04h 23h hardware reset maximum value, ffh = not supported 05h 00h hardware reset maximum exponent 2 n s 06h 23h software reset maximum value, ffh = not supported 07h 00h software reset maximum exponent 2 n s
january 8, 2014 S25FL512S_00_07 S25FL512S 127 data sheet table 11.15 cfi alternate vendor-specific extended query parameter 90h - hplc(sdr) (sheet 1 of 2) parameter relative byte address offset data description 00h 90h parameter id (latency code table) 01h 56h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 06h number of rows 03h 0eh row length in bytes 04h 46h start of header (row 1), ascii ?f? for frequency column header 05h 43h ascii ?c? for code column header 06h 03h read 3-byte address instruction 07h 13h read 4-byte address instruction 08h 0bh read fast 3-byte address instruction 09h 0ch read fast 4-byte address instruction 0ah 3bh read dual out 3-byte address instruction 0bh 3ch read dual out 4-byte address instruction 0ch 6bh read quad out 3-byte address instruction 0dh 6ch read quad out 4-byte address instruction 0eh bbh dual i/o read 3-byte address instruction 0fh bch dual i/o read 4-byte address instruction 10h ebh quad i/o read 3-byte address instruction 11h ech quad i/o read 4-byte address instruction 12h 32h start of row 2, sck frequency limit for this row (50 mhz) 13h 03h latency code for this row (11b) 14h 00h read mode cycles 15h 00h read latency cycles 16h 00h read fast mode cycles 17h 00h read fast latency cycles 18h 00h read dual out mode cycles 19h 00h read dual out latency cycles 1ah 00h read quad out mode cycles 1bh 00h read quad out latency cycles 1ch 00h dual i/o read mode cycles 1dh 04h dual i/o read latency cycles 1eh 02h quad i/o read mode cycles 1fh 01h quad i/o read latency cycles 20h 50h start of row 3, sck frequency limit for this row (80 mhz) 21h 00h latency code for this row (00b) 22h ffh read mode cycles (ffh = command not supported at this frequency) 23h ffh read latency cycles 24h 00h read fast mode cycles 25h 08h read fast latency cycles 26h 00h read dual out mode cycles 27h 08h read dual out latency cycles 28h 00h read quad out mode cycles 29h 08h read quad out latency cycles 2ah 00h dual i/o read mode cycles 2bh 04h dual i/o read latency cycles 2ch 02h quad i/o read mode cycles 2dh 04h quad i/o read latency cycles
128 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 2eh 5ah start of row 4, sck frequency limit for this row (90 mhz) 2fh 01h latency code for this row (01b) 30h ffh read mode cycles (ffh = command not supported at this frequency) 31h ffh read latency cycles 32h 00h read fast mode cycles 33h 08h read fast latency cycles 34h 00h read dual out mode cycles 35h 08h read dual out latency cycles 36h 00h read quad out mode cycles 37h 08h read quad out latency cycles 38h 00h dual i/o read mode cycles 39h 05h dual i/o read latency cycles 3ah 02h quad i/o read mode cycles 3bh 04h quad i/o read latency cycles 3ch 68h start of row 5, sck frequency limit for this row (104 mhz) 3dh 02h latency code for this row (10b) 3eh ffh read mode cycles (ffh = comm and not supported at this frequency) 3fh ffh read latency cycles 40h 00h read fast mode cycles 41h 08h read fast latency cycles 42h 00h read dual out mode cycles 43h 08h read dual out latency cycles 44h 00h read quad out mode cycles 45h 08h read quad out latency cycles 46h 00h dual i/o read mode cycles 47h 06h dual i/o read latency cycles 48h 02h quad i/o read mode cycles 49h 05h quad i/o read latency cycles 4ah 85h start of row 6, sck frequency limit for this row (133 mhz) 4bh 02h latency code for this row (10b) 4ch ffh read mode cycles (ffh = comm and not supported at this frequency) 4dh ffh read latency cycles 4eh 00h read fast mode cycles 4fh 08h read fast latency cycles 50h ffh read dual out mode cycles 51h ffh read dual out latency cycles 52h ffh read quad out mode cycles 53h ffh read quad out latency cycles 54h ffh dual i/o read mode cycles 55h ffh dual i/o read latency cycles 56h ffh quad i/o read mode cycles 57h ffh quad i/o read latency cycles table 11.15 cfi alternate vendor-specific extended query parameter 90h - hplc(sdr) (sheet 2 of 2) parameter relative byte address offset data description
january 8, 2014 S25FL512S_00_07 S25FL512S 129 data sheet table 11.16 cfi alternate vendor-specific extended query parameter 9ah - hplc ddr parameter relative byte address offset data description 00h 9ah parameter id (latency code table) 01h 2ah parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 05h number of rows 03h 08h row length in bytes 04h 46h start of header (row 1), ascii ?f? for frequency column header 05h 43h ascii ?c? for code column header 06h 0dh read fast ddr 3-byte address instruction 07h 0eh read fast ddr 4-byte address instruction 08h bdh ddr dual i/o read 3-byte address instruction 09h beh ddr dual i/o read 4-byte address instruction 0ah edh read ddr quad i/o 3-byte address instruction 0bh eeh read ddr quad i/o 4-byte address instruction 0ch 32h start of row 2, sck frequency limit for this row (50 mhz) 0dh 03h latency code for this row (11b) 0eh 00h read fast ddr mode cycles 0fh 04h read fast ddr latency cycles 10h 00h ddr dual i/o read mode cycles 11h 04h ddr dual i/o read latency cycles 12h 01h read ddr quad i/o mode cycles 13h 03h read ddr quad i/o latency cycles 14h 42h start of row 3, sck frequency limit for this row (66 mhz) 15h 00h latency code for this row (00b) 16h 00h read fast ddr mode cycles 17h 05h read fast ddr latency cycles 18h 00h ddr dual i/o read mode cycles 19h 06h ddr dual i/o read latency cycles 1ah 01h read ddr quad i/o mode cycles 1bh 06h read ddr quad i/o latency cycles 1ch 42h start of row 4, sck frequency limit for this row (66 mhz) 1dh 01h latency code for this row (01b) 1eh 00h read fast ddr mode cycles 1fh 06h read fast ddr latency cycles 20h 00h ddr dual i/o read mode cycles 21h 07h ddr dual i/o read latency cycles 22h 01h read ddr quad i/o mode cycles 23h 07h read ddr quad i/o latency cycles 24h 42h start of row 5, sck frequency limit for this row (66 mhz) 25h 02h latency code for this row (10b) 26h 00h read fast ddr mode cycles 27h 07h read fast ddr latency cycles 28h 00h ddr dual i/o read mode cycles 29h 08h ddr dual i/o read latency cycles 2ah 01h read ddr quad i/o mode cycles 2bh 08h read ddr quad i/o latency cycles
130 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet table 11.17 cfi alternate vendor-specific extended query parameter 90h - ehplc (sdr) (sheet 1 of 2) parameter relative byte address offset data description 00h 90h parameter id (latency code table) 01h 56h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 06h number of rows 03h 0eh row length in bytes 04h 46h start of header (row 1), ascii ?f? for frequency column header 05h 43h ascii ?c? for code column header 06h 03h read 3-byte address instruction 07h 13h read 4-byte address instruction 08h 0bh read fast 3-byte address instruction 09h 0ch read fast 4-byte address instruction 0ah 3bh read dual out 3-byte address instruction 0bh 3ch read dual out 4-byte address instruction 0ch 6bh read quad out 3-byte address instruction 0dh 6ch read quad out 4-byte address instruction 0eh bbh dual i/o read 3-byte address instruction 0fh bch dual i/o read 4-byte address instruction 10h ebh quad i/o read 3-byte address instruction 11h ech quad i/o read 4-byte address instruction 12h 32h start of row 2, sck frequency limit for this row (50 mhz) 13h 03h latency code for this row (11b) 14h 00h read mode cycles 15h 00h read latency cycles 16h 00h read fast mode cycles 17h 00h read fast latency cycles 18h 00h read dual out mode cycles 19h 00h read dual out latency cycles 1ah 00h read quad out mode cycles 1bh 00h read quad out latency cycles 1ch 04h dual i/o read mode cycles 1dh 00h dual i/o read latency cycles 1eh 02h quad i/o read mode cycles 1fh 01h quad i/o read latency cycles 20h 50h start of row 3, sck frequency limit for this row (80 mhz) 21h 00h latency code for this row (00b) 22h ffh read mode cycles (ffh = command not supported at this frequency) 23h ffh read latency cycles 24h 00h read fast mode cycles 25h 08h read fast latency cycles 26h 00h read dual out mode cycles 27h 08h read dual out latency cycles 28h 00h read quad out mode cycles 29h 08h read quad out latency cycles 2ah 04h dual i/o read mode cycles 2bh 00h dual i/o read latency cycles 2ch 02h quad i/o read mode cycles 2dh 04h quad i/o read latency cycles
january 8, 2014 S25FL512S_00_07 S25FL512S 131 data sheet 2eh 5ah start of row 4, sck frequency limit for this row (90 mhz) 2fh 01h latency code for this row (01b) 30h ffh read mode cycles (ffh = command not supported at this frequency) 31h ffh read latency cycles 32h 00h read fast mode cycles 33h 08h read fast latency cycles 34h 00h read dual out mode cycles 35h 08h read dual out latency cycles 36h 00h read quad out mode cycles 37h 08h read quad out latency cycles 38h 04h dual i/o read mode cycles 39h 01h dual i/o read latency cycles 3ah 02h quad i/o read mode cycles 3bh 04h quad i/o read latency cycles 3ch 68h start of row 5, sck frequency limit for this row (104 mhz) 3dh 02h latency code for this row (10b) 3eh ffh read mode cycles (ffh = comm and not supported at this frequency) 3fh ffh read latency cycles 40h 00h read fast mode cycles 41h 08h read fast latency cycles 42h 00h read dual out mode cycles 43h 08h read dual out latency cycles 44h 00h read quad out mode cycles 45h 08h read quad out latency cycles 46h 04h dual i/o read mode cycles 47h 02h dual i/o read latency cycles 48h 02h quad i/o read mode cycles 49h 05h quad i/o read latency cycles 4ah 85h start of row 6, sck frequency limit for this row (133 mhz) 4bh 02h latency code for this row (10b) 4ch ffh read mode cycles (ffh = comm and not supported at this frequency) 4dh ffh read latency cycles 4eh 00h read fast mode cycles 4fh 08h read fast latency cycles 50h ffh read dual out mode cycles 51h ffh read dual out latency cycles 52h ffh read quad out mode cycles 53h ffh read quad out latency cycles 54h ffh dual i/o read mode cycles 55h ffh dual i/o read latency cycles 56h ffh quad i/o read mode cycles 57h ffh quad i/o read latency cycles table 11.17 cfi alternate vendor-specific extended query parameter 90h - ehplc (sdr) (sheet 2 of 2) parameter relative byte address offset data description
132 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet table 11.18 cfi alternate vendor-specific extended query parameter 9ah - ehplc ddr parameter relative byte address offset data description 00h 9ah parameter id (latency code table) 01h 2ah parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 05h number of rows 03h 08h row length in bytes 04h 46h start of header (row 1), ascii ?f? for frequency column header 05h 43h ascii ?c? for code column header 06h 0dh read fast ddr 3-byte address instruction 07h 0eh read fast ddr 4-byte address instruction 08h bdh ddr dual i/o read 3-byte address instruction 09h beh ddr dual i/o read 4-byte address instruction 0ah edh read ddr quad i/o 3-byte address instruction 0bh eeh read ddr quad i/o 4-byte address instruction 0ch 32h start of row 2, sck frequency limit for this row (50 mhz) 0dh 03h latency code for this row (11b) 0eh 04h read fast ddr mode cycles 0fh 01h read fast ddr latency cycles 10h 02h ddr dual i/o read mode cycles 11h 02h ddr dual i/o read latency cycles 12h 01h read ddr quad i/o mode cycles 13h 03h read ddr quad i/o latency cycles 14h 42h start of row 3, sck frequency limit for this row (66 mhz) 15h 00h latency code for this row (00b) 16h 04h read fast ddr mode cycles 17h 02h read fast ddr latency cycles 18h 02h ddr dual i/o read mode cycles 19h 04h ddr dual i/o read latency cycles 1ah 01h read ddr quad i/o mode cycles 1bh 06h read ddr quad i/o latency cycles 1ch 42h start of row 4, sck frequency limit for this row (66 mhz) 1dh 01h latency code for this row (01b) 1eh 04h read fast ddr mode cycles 1fh 04h read fast ddr latency cycles 20h 02h ddr dual i/o read mode cycles 21h 05h ddr dual i/o read latency cycles 22h 01h read ddr quad i/o mode cycles 23h 07h read ddr quad i/o latency cycles 24h 42h start of row 5, sck frequency limit for this row (66 mhz) 25h 02h latency code for this row (10b) 26h 04h read fast ddr mode cycles 27h 05h read fast ddr latency cycles 28h 02h ddr dual i/o read mode cycles 29h 06h ddr dual i/o read latency cycles 2ah 01h read ddr quad i/o mode cycles 2bh 08h read ddr quad i/o latency cycles
january 8, 2014 S25FL512S_00_07 S25FL512S 133 data sheet this parameter type (parameter id f0h) may appear multiple times and have a different length each time. the parameter is used to reserve s pace in the id-cfi map or to force space (pad) to align a following parameter to a required boundary. 11.4 registers the register maps are copied in this section as a quick reference. see registers on page 57 for the full description of the register contents. table 11.19 cfi alternate vendor-specific extended query parameter f0h rfu parameter relative byte address offset data description 00h f0h parameter id (rfu) 01h 0fh parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h ffh rfu ... ffh rfu 10h ffh rfu table 11.20 status register-1 (sr1) bits field name function type default state description 7 srwd status register write disable non-volatile 0 1 = locks state of srwd, bp, and configuration register bits when wp# is low by ignoring wrr command 0 = no protection, even when wp# is low 6 p_err programming error occurred volatile, read only 0 1 = error occurred 0 = no error 5 e_err erase error occurred volatile, read only 0 1= error occurred 0 = no error 4 bp2 block protection volatile if cr1[3]=1, non-volatile if cr1[3]=0 1 if cr1[3]=1, 0 when shipped from spansion protects selected range of sectors (block) from program or erase 3 bp1 2 bp0 1 wel write enable latch volatile 0 1 = device accepts write registers (wrr), program or erase commands 0 = device ignores write registers (wrr), program or erase commands this bit is not affected by wrr, only wren and wrdi commands affect this bit. 0 wip write in progress volatile, read only 0 1= device busy, a write registers (wrr), program, erase or other operation is in progress 0 = ready device is in standby mode and can accept commands
134 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet table 11.21 configuration register (cr1) bits field name function type default state description 7 lc1 latency code non-volatile 0 selects number of initial read latency cycles see latency code tables 6 lc0 0 5 tbprot configures start of block protection otp 0 1 = bp starts at bottom (low address) 0 = bp starts at top (high address) 4 rfu rfu rfu 0 reserved for future use 3 bpnv configures bp2-0 in status register otp 0 1 = volatile 0 = non-volatile 2 rfu rfu rfu 0 reserved for future use 1 quad puts the device into quad i/o operation non-volatile 0 1 = quad 0 = dual or serial 0 freeze lock current state of bp2-0 bits in status register, tbprot in configuration register, and otp regions volatile 0 1 = block protection and otp locked 0 = block protection and otp un-locked table 11.22 status register-2 (sr2) bits field name function type default state description 7 rfu reserved 0 reserved for future use 6 rfu reserved 0 reserved for future use 5 rfu reserved 0 reserved for future use 4 rfu reserved 0 reserved for future use 3 rfu reserved 0 reserved for future use 2 rfu reserved 0 reserved for future use 1 es erase suspend volatile, read only 0 1 = in erase suspend mode. 0 = not in erase suspend mode. 0 ps program suspend volatile, read only 0 1 = in program suspend mode. 0 = not in program suspend mode. table 11.23 bank address register (bar) bits field name function type default state description 7 extadd extended address enable volatile 0b 1 = 4-byte (32-bits) addressing required from command. 0 = 3-byte (24-bits) addressing from command + bank address 6 to 2 rfu reserved volatile 00000b reserved for future use 1 ba25 bank address volatile 0 a25 for 512 mb device 0 rfu bank address volatile 0 rfu for lower density device
january 8, 2014 S25FL512S_00_07 S25FL512S 135 data sheet note: 1. default value depends on ordering part number, see initial delivery state on page 136 . table 11.24 asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use 8 rfu reserved otp (note 1) reserved for future use 7 rfu reserved otp (note 1) reserved for future use 6 rfu reserved otp 1 reserved for future use 5 rfu reserved otp (note 1) reserved for future use 4 rfu reserved otp (note 1) reserved for future use 3 rfu reserved otp (note 1) reserved for future use 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protection mode permanently enabled. 1 = persistent protection mode not permanently enabled. 0 rfu reserved otp 1 reserved for future use table 11.25 password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff- ffffffffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to zero. table 11.26 ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile persistent protection mode = 1 password protection mode = 0 0 = ppb array protected until next power cycle or hardware reset 1 = ppb array may be programmed or erased table 11.27 ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to ?0?, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd or ppbp command is erased to ?1?, not protecting that sector from program or erase operations. table 11.28 dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybp command is cleared to ?0?, protecting that sector from program or erase operations. ffh = dyb for the sector addressed by the dybrd or dybp command is set to ?1?, not protecting that sector from program or erase operations.
136 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet 11.5 initial delivery state the device is shipped from spansion with non-volatile bits set as follows: ? the entire memory array is erased: i.e. all bits are set to 1 (each byte contains ffh). ? the otp address space has the first 16 bytes progra mmed to a random number. all other bytes are erased to ffh. ? the sfdp address space contains the values as defi ned in the description of the sfdp address space. ? the id-cfi address space contains the values as defi ned in the description of the id-cfi address space. ? the status register 1 contains 00h (all sr1 bits are cleared to 0?s). ? the configuration regi ster 1 contains 00h. ? the autoboot register contains 00h. ? the password register contains ffffffff-ffffffffh ? all ppb bits are 1. ? the asp register contents depend on the ordering options selected: table 11.29 non-volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 nvdlp non-volatile data learning pattern otp 00h otp value that may be transferred to the host during ddr read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. table 11.30 volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 vdlp volatile data learning pattern volatile takes the value of nvdlr during por or reset volatile copy of the nvdlp used to enable and deliver the data learning pattern (dlp) to the outputs. the vdlp may be changed by the host during system operation. table 11.31 asp register content ordering part number model aspr default value 01, 21, 31, r1, a1, b1, c1, d1, 91, q1, 71, 61, 81 fe7fh k1, l1. s1, t1, y1, z1, m1, n1, u1, v1, w1, x1 fe4fh
january 8, 2014 S25FL512S_00_07 S25FL512S 137 data sheet ordering information 12. ordering information fl512s the ordering part number is formed by a valid combination of the following: notes: 1. ehplc = enhanced high performance latency code table. 2. hplc = high performance latency code table. 3. uniform 256-kb sectors = all sectors are uniform 256-kb with a 512b programming buffer. s25fl 512 s ag m f i 0 0 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (sector type) 1 = uniform 256-kb sectors model number (latency type, package details, reset# and v io support) 0 = ehplc, so footprint 2 = ehplc, 5 x 5 ball bga footprint 3 = ehplc, 4 x 6 ball bga footprint g = ehplc, so footprint with reset# r = ehplc, so footprint with reset# and v io a = ehplc, 5 x 5 ball bga footprint with reset# and v io b = ehplc, 4 x 6 ball bga footprint with reset# and v io c = ehplc, 5 x 5 ball bga footprint with reset# d = ehplc, 4 x 6 ball bga footprint with reset# 9 = hplc, so footprint 4 = hplc, 5 x 5 ball bga footprint 8 = hplc, 4 x 6 ball bga footprint h = hplc, so footprint with reset# q = hplc, so footprint with reset# and v io 7 = hplc, 5 x 5 ball bga footprint with reset# and v io 6 = hplc, 4 x 6 ball bga footprint with reset# and v io e = hplc, 5 x 5 ball bga footprint with reset# f = hplc, 4 x 6 ball bga footprint with reset# temperature range i = industrial (?40c to + 85c) v = automotive in-cabin (?40c to + 105c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin so package b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed ag = 133 mhz dp = 66 mhz ddr ds = 80 mhz ddr device technology s = 0.065 m mirrorbit process technology density 512 = 512 mbit device family s25fl spansion memory 3.0 volt-only, serial peripheral interface (spi) flash memory
138 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. note: 1. example, S25FL512Sagmfi000 package marking would be fl512saif00. 13. contacting spansion obtain the latest list of company locations and contact information at: http://www.spansion.com/about/pages/locations.aspx valid combinations base ordering part number speed option package and temperature model number packing type package marking (1) S25FL512S ag mfi, mfv 01, g1, r1 0, 1, 3 fl512s + a + (temp) + f + (model number) dp mfi, mfv 01, g1 fl512s + d + (temp) + f + (model number) ds mfv, mfi 01 0, 1, 3 fl512s + s + (temp) + f + (model number) ag bhi, bhv 21, 31, a1, b1, c1, d1 0, 3 fl512s + a + (temp) + h + (model number) dp bhi, bhv 21, 31, c1, d1 fl512s + d + (temp) + h + (model number) ds mfv, mfi 01 0, 1, 3 fl512s + s + (temp) + f + (model number) bhi, bhv 21 0, 3 fl512s + s + (temp) + h + (model number)
january 8, 2014 S25FL512S_00_07 S25FL512S 139 data sheet 14. revision history section description revision 01 (december 20, 2011) initial release revision 02 (march 2, 2012) general changed data sheet designation from advance information to preliminary performance summary current consumption table: corrected serial read 50 mhz and serial read 133 mhz values dc characteristics dc characteristics table: corrected i cc1 values sdr ac characteristics ac characteristics (single die package, v io = v cc 2.7v to 3.6v) table: corrected t csh and t su max values ac characteristics (single die package, v io 1.65v to 2.7v, v cc 2.7v to 3.6v) table: corrected t csh and t su max values embedded algorithm performance ta b l e s program and erase performance table: corrected t w typ and max values device id and common flash interface (id-cfi) address map updated table: cfi alternate vendor-s pecific extended query parameter 0 revision 03 (may 2, 2012) global added 105c updates ordering information updated valid combinations table embedded algorithm performance ta b l e s updated table: program and erase performance revision 04 (june 13, 2012) sdr ac characteristics updated t ho value from 0 min to 2 ns min revision 05 (april 12, 2013) global data sheet designation updated from preliminary to full production revision 06 (december 20, 2013) global 80 mhz ddr read operation added performance summary updated maximum read rates ddr (v io = v cc = 3v to 3.6v) table current consumption table: added quad ddr read 80 mhz migration notes fl generations comparison table: updated ddr values for fl-s sdr ac characteristics updated clock timing figure ddr ac characteristics updated ac characteristics ? ddr operation table ddr output timing updated spi ddr data valid window figure and notes ordering information added 80 mhz to speed option valid combinations table: added ds to speed option revision 07 (january 8, 2014) ddr ac characteristics removed ac char acteristics 80 mhz operation table
140 S25FL512S S25FL512S_00_07 january 8, 2014 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2011-2014 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners.

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